drm/i915: delete gpu reloc code
It's already removed, this just garbage collects it all. v2: Rebase over s/GEN/GRAPHICS_VER/ v3: Also ditch eb.reloc_pool and eb.reloc_context (Maarten) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Link: https://patchwork.freedesktop.org/patch/msgid/20210803124833.3817354-2-daniel.vetter@ffwll.ch
This commit is contained in:
Daniel Vetter
parent
ce13c78fa9
commit
8e02cceb1f
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@ -277,16 +277,8 @@ struct i915_execbuffer {
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bool has_llc : 1;
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bool has_fence : 1;
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bool needs_unfenced : 1;
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struct i915_request *rq;
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u32 *rq_cmd;
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unsigned int rq_size;
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struct intel_gt_buffer_pool_node *pool;
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} reloc_cache;
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struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for -EDEADLK handling */
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struct intel_context *reloc_context;
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u64 invalid_flags; /** Set of execobj.flags that are invalid */
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u64 batch_len; /** Length of batch within object */
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@ -1024,8 +1016,6 @@ static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
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static void eb_destroy(const struct i915_execbuffer *eb)
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{
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GEM_BUG_ON(eb->reloc_cache.rq);
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if (eb->lut_size > 0)
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kfree(eb->buckets);
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}
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@ -1037,14 +1027,6 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
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return gen8_canonical_addr((int)reloc->delta + target->node.start);
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}
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static void reloc_cache_clear(struct reloc_cache *cache)
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{
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cache->rq = NULL;
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cache->rq_cmd = NULL;
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cache->pool = NULL;
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cache->rq_size = 0;
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}
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static void reloc_cache_init(struct reloc_cache *cache,
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struct drm_i915_private *i915)
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{
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@ -1057,7 +1039,6 @@ static void reloc_cache_init(struct reloc_cache *cache,
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cache->has_fence = cache->graphics_ver < 4;
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cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
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cache->node.flags = 0;
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reloc_cache_clear(cache);
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}
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static inline void *unmask_page(unsigned long p)
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@ -1079,48 +1060,10 @@ static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
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return &i915->ggtt;
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}
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static void reloc_cache_put_pool(struct i915_execbuffer *eb, struct reloc_cache *cache)
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{
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if (!cache->pool)
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return;
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/*
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* This is a bit nasty, normally we keep objects locked until the end
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* of execbuffer, but we already submit this, and have to unlock before
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* dropping the reference. Fortunately we can only hold 1 pool node at
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* a time, so this should be harmless.
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*/
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i915_gem_ww_unlock_single(cache->pool->obj);
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intel_gt_buffer_pool_put(cache->pool);
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cache->pool = NULL;
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}
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static void reloc_gpu_flush(struct i915_execbuffer *eb, struct reloc_cache *cache)
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{
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struct drm_i915_gem_object *obj = cache->rq->batch->obj;
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GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32));
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cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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i915_gem_object_unpin_map(obj);
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intel_gt_chipset_flush(cache->rq->engine->gt);
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i915_request_add(cache->rq);
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reloc_cache_put_pool(eb, cache);
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reloc_cache_clear(cache);
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eb->reloc_pool = NULL;
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}
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static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
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{
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void *vaddr;
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if (cache->rq)
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reloc_gpu_flush(eb, cache);
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if (!cache->vaddr)
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return;
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@ -1302,295 +1245,6 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
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*addr = value;
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}
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static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
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{
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struct drm_i915_gem_object *obj = vma->obj;
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int err;
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assert_vma_held(vma);
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if (obj->cache_dirty & ~obj->cache_coherent)
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i915_gem_clflush_object(obj, 0);
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obj->write_domain = 0;
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err = i915_request_await_object(rq, vma->obj, true);
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if (err == 0)
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err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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return err;
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}
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static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
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struct intel_engine_cs *engine,
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struct i915_vma *vma,
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unsigned int len)
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{
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struct reloc_cache *cache = &eb->reloc_cache;
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struct intel_gt_buffer_pool_node *pool = eb->reloc_pool;
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struct i915_request *rq;
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struct i915_vma *batch;
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u32 *cmd;
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int err;
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if (!pool) {
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pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE,
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cache->has_llc ?
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I915_MAP_WB :
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I915_MAP_WC);
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if (IS_ERR(pool))
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return PTR_ERR(pool);
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}
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eb->reloc_pool = NULL;
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err = i915_gem_object_lock(pool->obj, &eb->ww);
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if (err)
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goto err_pool;
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cmd = i915_gem_object_pin_map(pool->obj, pool->type);
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if (IS_ERR(cmd)) {
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err = PTR_ERR(cmd);
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goto err_pool;
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}
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intel_gt_buffer_pool_mark_used(pool);
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memset32(cmd, 0, pool->obj->base.size / sizeof(u32));
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batch = i915_vma_instance(pool->obj, vma->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto err_unmap;
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}
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err = i915_vma_pin_ww(batch, &eb->ww, 0, 0, PIN_USER | PIN_NONBLOCK);
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if (err)
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goto err_unmap;
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if (engine == eb->context->engine) {
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rq = i915_request_create(eb->context);
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} else {
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struct intel_context *ce = eb->reloc_context;
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if (!ce) {
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ce = intel_context_create(engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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goto err_unpin;
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}
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i915_vm_put(ce->vm);
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ce->vm = i915_vm_get(eb->context->vm);
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eb->reloc_context = ce;
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}
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err = intel_context_pin_ww(ce, &eb->ww);
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if (err)
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goto err_unpin;
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rq = i915_request_create(ce);
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intel_context_unpin(ce);
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}
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto err_unpin;
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}
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err = intel_gt_buffer_pool_mark_active(pool, rq);
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if (err)
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goto err_request;
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err = reloc_move_to_gpu(rq, vma);
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if (err)
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goto err_request;
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err = eb->engine->emit_bb_start(rq,
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batch->node.start, PAGE_SIZE,
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cache->graphics_ver > 5 ? 0 : I915_DISPATCH_SECURE);
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if (err)
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goto skip_request;
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assert_vma_held(batch);
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err = i915_request_await_object(rq, batch->obj, false);
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if (err == 0)
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err = i915_vma_move_to_active(batch, rq, 0);
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if (err)
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goto skip_request;
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rq->batch = batch;
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i915_vma_unpin(batch);
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cache->rq = rq;
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cache->rq_cmd = cmd;
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cache->rq_size = 0;
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cache->pool = pool;
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/* Return with batch mapping (cmd) still pinned */
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return 0;
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skip_request:
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i915_request_set_error_once(rq, err);
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err_request:
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i915_request_add(rq);
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err_unpin:
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i915_vma_unpin(batch);
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err_unmap:
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i915_gem_object_unpin_map(pool->obj);
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err_pool:
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eb->reloc_pool = pool;
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return err;
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}
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static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
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{
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return engine->class != VIDEO_DECODE_CLASS || GRAPHICS_VER(engine->i915) != 6;
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}
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static u32 *reloc_gpu(struct i915_execbuffer *eb,
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struct i915_vma *vma,
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unsigned int len)
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{
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struct reloc_cache *cache = &eb->reloc_cache;
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u32 *cmd;
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if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
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reloc_gpu_flush(eb, cache);
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if (unlikely(!cache->rq)) {
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int err;
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struct intel_engine_cs *engine = eb->engine;
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/* If we need to copy for the cmdparser, we will stall anyway */
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if (eb_use_cmdparser(eb))
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return ERR_PTR(-EWOULDBLOCK);
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if (!reloc_can_use_engine(engine)) {
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engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
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if (!engine)
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return ERR_PTR(-ENODEV);
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}
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err = __reloc_gpu_alloc(eb, engine, vma, len);
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if (unlikely(err))
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return ERR_PTR(err);
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}
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cmd = cache->rq_cmd + cache->rq_size;
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cache->rq_size += len;
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return cmd;
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}
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static inline bool use_reloc_gpu(struct i915_vma *vma)
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{
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if (DBG_FORCE_RELOC == FORCE_GPU_RELOC)
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return true;
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if (DBG_FORCE_RELOC)
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return false;
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return !dma_resv_test_signaled(vma->resv, true);
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}
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static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset)
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{
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struct page *page;
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unsigned long addr;
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GEM_BUG_ON(vma->pages != vma->obj->mm.pages);
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page = i915_gem_object_get_page(vma->obj, offset >> PAGE_SHIFT);
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addr = PFN_PHYS(page_to_pfn(page));
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GEM_BUG_ON(overflows_type(addr, u32)); /* expected dma32 */
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return addr + offset_in_page(offset);
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}
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static int __reloc_entry_gpu(struct i915_execbuffer *eb,
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struct i915_vma *vma,
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u64 offset,
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u64 target_addr)
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{
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const unsigned int ver = eb->reloc_cache.graphics_ver;
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unsigned int len;
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u32 *batch;
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u64 addr;
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if (ver >= 8)
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len = offset & 7 ? 8 : 5;
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else if (ver >= 4)
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len = 4;
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else
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len = 3;
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batch = reloc_gpu(eb, vma, len);
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if (batch == ERR_PTR(-EDEADLK))
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return -EDEADLK;
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else if (IS_ERR(batch))
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return false;
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addr = gen8_canonical_addr(vma->node.start + offset);
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if (ver >= 8) {
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if (offset & 7) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = lower_32_bits(addr);
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*batch++ = upper_32_bits(addr);
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*batch++ = lower_32_bits(target_addr);
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addr = gen8_canonical_addr(addr + 4);
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = lower_32_bits(addr);
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*batch++ = upper_32_bits(addr);
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*batch++ = upper_32_bits(target_addr);
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} else {
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*batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
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*batch++ = lower_32_bits(addr);
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*batch++ = upper_32_bits(addr);
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*batch++ = lower_32_bits(target_addr);
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*batch++ = upper_32_bits(target_addr);
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}
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} else if (ver >= 6) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = 0;
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*batch++ = addr;
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*batch++ = target_addr;
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} else if (IS_I965G(eb->i915)) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = 0;
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*batch++ = vma_phys_addr(vma, offset);
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*batch++ = target_addr;
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} else if (ver >= 4) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
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*batch++ = 0;
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*batch++ = addr;
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*batch++ = target_addr;
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} else if (ver >= 3 &&
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!(IS_I915G(eb->i915) || IS_I915GM(eb->i915))) {
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*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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*batch++ = addr;
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*batch++ = target_addr;
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} else {
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*batch++ = MI_STORE_DWORD_IMM;
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*batch++ = vma_phys_addr(vma, offset);
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*batch++ = target_addr;
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}
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return true;
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}
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static int __maybe_unused reloc_entry_gpu(struct i915_execbuffer *eb,
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struct i915_vma *vma,
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u64 offset,
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u64 target_addr)
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{
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if (eb->reloc_cache.vaddr)
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return false;
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if (!use_reloc_gpu(vma))
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return false;
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return __reloc_entry_gpu(eb, vma, offset, target_addr);
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}
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static u64
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relocate_entry(struct i915_vma *vma,
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const struct drm_i915_gem_relocation_entry *reloc,
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@ -3153,8 +2807,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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eb.exec = exec;
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eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
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eb.vma[0].vma = NULL;
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eb.reloc_pool = eb.batch_pool = NULL;
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eb.reloc_context = NULL;
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eb.batch_pool = NULL;
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eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
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reloc_cache_init(&eb.reloc_cache, eb.i915);
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@ -3252,9 +2905,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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batch = eb.batch->vma;
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/* All GPU relocation batches must be submitted prior to the user rq */
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GEM_BUG_ON(eb.reloc_cache.rq);
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/* Allocate a request for this batch buffer nice and early. */
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eb.request = i915_request_create(eb.context);
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if (IS_ERR(eb.request)) {
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@ -3345,10 +2995,6 @@ err_vma:
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if (eb.batch_pool)
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intel_gt_buffer_pool_put(eb.batch_pool);
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if (eb.reloc_pool)
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intel_gt_buffer_pool_put(eb.reloc_pool);
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if (eb.reloc_context)
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intel_context_put(eb.reloc_context);
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err_engine:
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eb_put_engine(&eb);
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err_context:
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@ -3462,7 +3108,3 @@ end:;
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kvfree(exec2_list);
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return err;
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftests/i915_gem_execbuffer.c"
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#endif
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@ -38,7 +38,6 @@ selftest(gem, i915_gem_live_selftests)
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selftest(evict, i915_gem_evict_live_selftests)
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selftest(hugepages, i915_gem_huge_page_live_selftests)
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selftest(gem_contexts, i915_gem_context_live_selftests)
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selftest(gem_execbuf, i915_gem_execbuffer_live_selftests)
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selftest(client, i915_gem_client_blt_live_selftests)
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selftest(gem_migrate, i915_gem_migrate_live_selftests)
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selftest(reset, intel_reset_live_selftests)
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