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clk: imx6sl: remove clks_init_on array
Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. ARM clock is busy divider type which has the CLK_IS_CRITICAL flag set by default when registered. IPG clock has no clock gate and its parent AHB clock is busy divider type, so no need to add CLK_IS_CRITICAL flag for IPG clock. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1 changed files with 0 additions and 12 deletions
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@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data;
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static void __iomem *ccm_base;
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static void __iomem *anatop_base;
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static const u32 clks_init_on[] __initconst = {
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IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
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};
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/*
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* ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
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* during WAIT mode entry process could cause cache memory
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@ -195,7 +191,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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int ret;
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clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@ -426,13 +421,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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pr_warn("%s: failed to set AHB clock rate %d!\n",
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__func__, ret);
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/*
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* Make sure those always on clocks are enabled to maintain the correct
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* usecount and enabling/disabling of parent PLLs.
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*/
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for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
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clk_prepare_enable(clks[clks_init_on[i]]);
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if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
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clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
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clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
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