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[ARM] 3330/1: S3C24XX - move UPLL to main clock
Patch from Ben Dooks Move the UPLL clock registration to the central clock file, and add an enable method Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
766636cc36
commit
8e40a2f91c
2 changed files with 38 additions and 19 deletions
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@ -38,6 +38,7 @@
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#include <linux/ioport.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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@ -200,6 +201,28 @@ EXPORT_SYMBOL(clk_round_rate);
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EXPORT_SYMBOL(clk_set_rate);
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EXPORT_SYMBOL(clk_get_parent);
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/* base clock enable */
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static int s3c24xx_upll_enable(struct clk *clk, int enable)
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{
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unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
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unsigned long orig = clkslow;
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if (enable)
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clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
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else
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clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
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__raw_writel(clkslow, S3C2410_CLKSLOW);
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/* if we started the UPLL, then allow to settle */
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if (enable && !(orig & S3C2410_CLKSLOW_UCLK_OFF))
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udelay(200);
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return 0;
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}
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/* base clocks */
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static struct clk clk_xtal = {
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@ -210,6 +233,14 @@ static struct clk clk_xtal = {
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.ctrlbit = 0,
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};
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static struct clk clk_upll = {
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.name = "upll",
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.id = -1,
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.parent = NULL,
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.enable = s3c24xx_upll_enable,
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.ctrlbit = 0,
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};
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static struct clk clk_f = {
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.name = "fclk",
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.id = -1,
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@ -262,7 +293,7 @@ struct clk s3c24xx_uclk = {
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};
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/* clock definitions */
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/* standard clock definitions */
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static struct clk init_clocks[] = {
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{
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@ -396,6 +427,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
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unsigned long hclk,
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unsigned long pclk)
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{
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unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
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unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
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struct clk *clkp = init_clocks;
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int ptr;
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@ -406,6 +438,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
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/* initialise the main system clocks */
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clk_xtal.rate = xtal;
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clk_upll.rate = s3c2410_get_pll(upllcon, xtal);
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clk_h.rate = hclk;
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clk_p.rate = pclk;
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@ -439,6 +472,9 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
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if (s3c24xx_register_clock(&clk_xtal) < 0)
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printk(KERN_ERR "failed to register master xtal\n");
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if (s3c24xx_register_clock(&clk_upll) < 0)
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printk(KERN_ERR "failed to register upll clock\n");
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if (s3c24xx_register_clock(&clk_f) < 0)
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printk(KERN_ERR "failed to register cpu fclk\n");
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@ -45,11 +45,6 @@
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/* S3C2440 extended clock support */
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static struct clk s3c2440_clk_upll = {
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.name = "upll",
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.id = -1,
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};
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static struct clk s3c2440_clk_cam = {
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.name = "camif",
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.id = -1,
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@ -66,22 +61,11 @@ static struct clk s3c2440_clk_ac97 = {
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static int s3c2440_clk_add(struct sys_device *sysdev)
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{
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unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
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unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
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struct clk *clk_h;
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struct clk *clk_p;
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struct clk *clk_xtal;
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clk_xtal = clk_get(NULL, "xtal");
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if (IS_ERR(clk_xtal)) {
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printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
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return -EINVAL;
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}
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s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
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printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
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print_mhz(s3c2440_clk_upll.rate),
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printk("S3C2440: Clock Support, DVS %s\n",
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(camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
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clk_p = clk_get(NULL, "pclk");
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@ -97,7 +81,6 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
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s3c24xx_register_clock(&s3c2440_clk_ac97);
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s3c24xx_register_clock(&s3c2440_clk_cam);
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s3c24xx_register_clock(&s3c2440_clk_upll);
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clk_disable(&s3c2440_clk_ac97);
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clk_disable(&s3c2440_clk_cam);
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