mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-30 14:19:16 +00:00
interconnect: qcom: sm8250: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-18-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Konrad Dybcio
Georgi Djakov
parent
670699a422
commit
8e509d66df
1 changed files with 240 additions and 27 deletions
|
|
@ -1395,33 +1395,246 @@ static struct qcom_icc_node qup2_core_slave = {
|
|||
.buswidth = 4,
|
||||
};
|
||||
|
||||
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
|
||||
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
|
||||
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
|
||||
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
|
||||
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
|
||||
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
|
||||
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
|
||||
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
|
||||
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master);
|
||||
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
|
||||
DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
|
||||
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
|
||||
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
|
||||
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
|
||||
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
|
||||
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
|
||||
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
|
||||
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
|
||||
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
|
||||
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
|
||||
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
|
||||
DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
|
||||
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
|
||||
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
|
||||
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
|
||||
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
|
||||
DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
|
||||
static struct qcom_icc_bcm bcm_acv = {
|
||||
.name = "ACV",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0 = {
|
||||
.name = "MC0",
|
||||
.keepalive = true,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0 = {
|
||||
.name = "SH0",
|
||||
.keepalive = true,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm0 = {
|
||||
.name = "MM0",
|
||||
.keepalive = true,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_hf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_ce0 = {
|
||||
.name = "CE0",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qxm_crypto },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm1 = {
|
||||
.name = "MM1",
|
||||
.keepalive = false,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh2 = {
|
||||
.name = "SH2",
|
||||
.keepalive = false,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm2 = {
|
||||
.name = "MM2",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_sf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_qup0 = {
|
||||
.name = "QUP0",
|
||||
.keepalive = false,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh3 = {
|
||||
.name = "SH3",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_cmpnoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm3 = {
|
||||
.name = "MM3",
|
||||
.keepalive = false,
|
||||
.num_nodes = 5,
|
||||
.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh4 = {
|
||||
.name = "SH4",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &chm_apps },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn0 = {
|
||||
.name = "SN0",
|
||||
.keepalive = true,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_gemnoc_sf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_co0 = {
|
||||
.name = "CO0",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_cdsp_mem_noc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_cn0 = {
|
||||
.name = "CN0",
|
||||
.keepalive = true,
|
||||
.num_nodes = 52,
|
||||
.nodes = { &qnm_snoc,
|
||||
&xm_qdss_dap,
|
||||
&qhs_a1_noc_cfg,
|
||||
&qhs_a2_noc_cfg,
|
||||
&qhs_ahb2phy0,
|
||||
&qhs_ahb2phy1,
|
||||
&qhs_aoss,
|
||||
&qhs_camera_cfg,
|
||||
&qhs_clk_ctl,
|
||||
&qhs_compute_dsp,
|
||||
&qhs_cpr_cx,
|
||||
&qhs_cpr_mmcx,
|
||||
&qhs_cpr_mx,
|
||||
&qhs_crypto0_cfg,
|
||||
&qhs_cx_rdpm,
|
||||
&qhs_dcc_cfg,
|
||||
&qhs_ddrss_cfg,
|
||||
&qhs_display_cfg,
|
||||
&qhs_gpuss_cfg,
|
||||
&qhs_imem_cfg,
|
||||
&qhs_ipa,
|
||||
&qhs_ipc_router,
|
||||
&qhs_lpass_cfg,
|
||||
&qhs_mnoc_cfg,
|
||||
&qhs_npu_cfg,
|
||||
&qhs_pcie0_cfg,
|
||||
&qhs_pcie1_cfg,
|
||||
&qhs_pcie_modem_cfg,
|
||||
&qhs_pdm,
|
||||
&qhs_pimem_cfg,
|
||||
&qhs_prng,
|
||||
&qhs_qdss_cfg,
|
||||
&qhs_qspi,
|
||||
&qhs_qup0,
|
||||
&qhs_qup1,
|
||||
&qhs_qup2,
|
||||
&qhs_sdc2,
|
||||
&qhs_sdc4,
|
||||
&qhs_snoc_cfg,
|
||||
&qhs_tcsr,
|
||||
&qhs_tlmm0,
|
||||
&qhs_tlmm1,
|
||||
&qhs_tlmm2,
|
||||
&qhs_tsif,
|
||||
&qhs_ufs_card_cfg,
|
||||
&qhs_ufs_mem_cfg,
|
||||
&qhs_usb3_0,
|
||||
&qhs_usb3_1,
|
||||
&qhs_venus_cfg,
|
||||
&qhs_vsense_ctrl_cfg,
|
||||
&qns_cnoc_a2noc,
|
||||
&srvc_cnoc
|
||||
},
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn1 = {
|
||||
.name = "SN1",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qxs_imem },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn2 = {
|
||||
.name = "SN2",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_gemnoc_gc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_co2 = {
|
||||
.name = "CO2",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_npu },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn3 = {
|
||||
.name = "SN3",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qxs_pimem },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn4 = {
|
||||
.name = "SN4",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &xs_qdss_stm },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn5 = {
|
||||
.name = "SN5",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &xs_pcie_modem },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn6 = {
|
||||
.name = "SN6",
|
||||
.keepalive = false,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &xs_pcie_0, &xs_pcie_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn7 = {
|
||||
.name = "SN7",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_aggre1_noc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn8 = {
|
||||
.name = "SN8",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_aggre2_noc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn9 = {
|
||||
.name = "SN9",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_gemnoc_pcie },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn11 = {
|
||||
.name = "SN11",
|
||||
.keepalive = false,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_gemnoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sn12 = {
|
||||
.name = "SN12",
|
||||
.keepalive = false,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
|
||||
&bcm_sn12,
|
||||
|
|
|
|||
Loading…
Reference in a new issue