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iommu/arm-smmu: Reintroduce locking around TLB sync operations
Commit523d7423e2
("iommu/arm-smmu: Remove io-pgtable spinlock") removed the locking used to serialise map/unmap calls into the io-pgtable code from the ARM SMMU driver. This is good for performance, but opens us up to a nasty race with TLB syncs because the TLB sync register is shared within a context bank (or even globally for stage-2 on SMMUv1). There are two cases to consider: 1. A CPU can be spinning on the completion of a TLB sync, take an interrupt which issues a subsequent TLB sync, and then report a timeout on return from the interrupt. 2. A CPU can be spinning on the completion of a TLB sync, but other CPUs can continuously issue additional TLB syncs in such a way that the backoff logic reports a timeout. Rather than fix this by spinning for completion of prior TLB syncs before issuing a new one (which may suffer from fairness issues on large systems), instead reintroduce locking around TLB sync operations in the ARM SMMU driver. Fixes:523d7423e2
("iommu/arm-smmu: Remove io-pgtable spinlock") Cc: Robin Murphy <robin.murphy@arm.com> Reported-by: Ray Jui <ray.jui@broadcom.com> Tested-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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parent
5771a8c088
commit
8e517e762a
1 changed files with 10 additions and 1 deletions
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@ -400,6 +400,8 @@ struct arm_smmu_device {
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u32 cavium_id_base; /* Specific to Cavium */
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spinlock_t global_sync_lock;
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/* IOMMU core code handle */
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struct iommu_device iommu;
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};
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@ -436,7 +438,7 @@ struct arm_smmu_domain {
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struct arm_smmu_cfg cfg;
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enum arm_smmu_domain_stage stage;
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struct mutex init_mutex; /* Protects smmu pointer */
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spinlock_t cb_lock; /* Serialises ATS1* ops */
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spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */
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struct iommu_domain domain;
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};
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@ -602,9 +604,12 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu,
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static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu)
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{
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void __iomem *base = ARM_SMMU_GR0(smmu);
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unsigned long flags;
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spin_lock_irqsave(&smmu->global_sync_lock, flags);
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__arm_smmu_tlb_sync(smmu, base + ARM_SMMU_GR0_sTLBGSYNC,
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base + ARM_SMMU_GR0_sTLBGSTATUS);
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spin_unlock_irqrestore(&smmu->global_sync_lock, flags);
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}
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static void arm_smmu_tlb_sync_context(void *cookie)
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@ -612,9 +617,12 @@ static void arm_smmu_tlb_sync_context(void *cookie)
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struct arm_smmu_domain *smmu_domain = cookie;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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void __iomem *base = ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx);
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unsigned long flags;
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spin_lock_irqsave(&smmu_domain->cb_lock, flags);
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__arm_smmu_tlb_sync(smmu, base + ARM_SMMU_CB_TLBSYNC,
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base + ARM_SMMU_CB_TLBSTATUS);
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spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
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}
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static void arm_smmu_tlb_sync_vmid(void *cookie)
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@ -1925,6 +1933,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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smmu->num_mapping_groups = size;
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mutex_init(&smmu->stream_map_mutex);
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spin_lock_init(&smmu->global_sync_lock);
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if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) {
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smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L;
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