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synced 2024-09-06 02:50:43 +00:00
[BNX2]: Add 1-shot MSI handler for 5709.
The 5709 supports the one-shot MSI handler similar to some of the tg3 chips. In this mode, the MSI disables itself automatically until it is re-enabled at the end of NAPI poll. Put the request_irq/free_irq logic in common procedures. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
da3e4fbed2
commit
8e6a72c435
2 changed files with 81 additions and 41 deletions
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@ -2261,6 +2261,23 @@ bnx2_msi(int irq, void *dev_instance)
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return IRQ_HANDLED;
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}
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static irqreturn_t
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bnx2_msi_1shot(int irq, void *dev_instance)
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{
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struct net_device *dev = dev_instance;
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struct bnx2 *bp = netdev_priv(dev);
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prefetch(bp->status_blk);
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/* Return here if interrupt is disabled. */
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if (unlikely(atomic_read(&bp->intr_sem) != 0))
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return IRQ_HANDLED;
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netif_rx_schedule(dev);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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bnx2_interrupt(int irq, void *dev_instance)
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{
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@ -3759,13 +3776,17 @@ bnx2_init_chip(struct bnx2 *bp)
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REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
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if (CHIP_ID(bp) == CHIP_ID_5706_A1)
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REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
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val = BNX2_HC_CONFIG_COLLECT_STATS;
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else {
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REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
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BNX2_HC_CONFIG_TX_TMR_MODE |
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BNX2_HC_CONFIG_COLLECT_STATS);
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val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
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BNX2_HC_CONFIG_COLLECT_STATS;
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}
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if (bp->flags & ONE_SHOT_MSI_FLAG)
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val |= BNX2_HC_CONFIG_ONE_SHOT;
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REG_WR(bp, BNX2_HC_CONFIG, val);
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/* Clear internal stats counters. */
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REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
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@ -4610,6 +4631,38 @@ bnx2_timer(unsigned long data)
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mod_timer(&bp->timer, jiffies + bp->current_interval);
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}
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static int
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bnx2_request_irq(struct bnx2 *bp)
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{
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struct net_device *dev = bp->dev;
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int rc = 0;
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if (bp->flags & USING_MSI_FLAG) {
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irq_handler_t fn = bnx2_msi;
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if (bp->flags & ONE_SHOT_MSI_FLAG)
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fn = bnx2_msi_1shot;
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rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev);
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} else
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rc = request_irq(bp->pdev->irq, bnx2_interrupt,
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IRQF_SHARED, dev->name, dev);
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return rc;
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}
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static void
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bnx2_free_irq(struct bnx2 *bp)
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{
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struct net_device *dev = bp->dev;
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if (bp->flags & USING_MSI_FLAG) {
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free_irq(bp->pdev->irq, dev);
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pci_disable_msi(bp->pdev);
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bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
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} else
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free_irq(bp->pdev->irq, dev);
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}
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/* Called with rtnl_lock */
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static int
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bnx2_open(struct net_device *dev)
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@ -4626,24 +4679,15 @@ bnx2_open(struct net_device *dev)
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if (rc)
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return rc;
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if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
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(CHIP_ID(bp) != CHIP_ID_5706_A1) &&
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!disable_msi) {
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if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) {
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if (pci_enable_msi(bp->pdev) == 0) {
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bp->flags |= USING_MSI_FLAG;
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rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
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dev);
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}
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else {
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rc = request_irq(bp->pdev->irq, bnx2_interrupt,
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IRQF_SHARED, dev->name, dev);
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bp->flags |= ONE_SHOT_MSI_FLAG;
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}
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}
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else {
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rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED,
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dev->name, dev);
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}
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rc = bnx2_request_irq(bp);
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if (rc) {
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bnx2_free_mem(bp);
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return rc;
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@ -4652,11 +4696,7 @@ bnx2_open(struct net_device *dev)
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rc = bnx2_init_nic(bp);
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if (rc) {
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free_irq(bp->pdev->irq, dev);
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if (bp->flags & USING_MSI_FLAG) {
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pci_disable_msi(bp->pdev);
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bp->flags &= ~USING_MSI_FLAG;
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}
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bnx2_free_irq(bp);
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bnx2_free_skbs(bp);
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bnx2_free_mem(bp);
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return rc;
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@ -4680,16 +4720,13 @@ bnx2_open(struct net_device *dev)
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bp->dev->name);
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bnx2_disable_int(bp);
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free_irq(bp->pdev->irq, dev);
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pci_disable_msi(bp->pdev);
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bp->flags &= ~USING_MSI_FLAG;
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bnx2_free_irq(bp);
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rc = bnx2_init_nic(bp);
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if (!rc) {
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rc = request_irq(bp->pdev->irq, bnx2_interrupt,
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IRQF_SHARED, dev->name, dev);
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}
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if (!rc)
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rc = bnx2_request_irq(bp);
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if (rc) {
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bnx2_free_skbs(bp);
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bnx2_free_mem(bp);
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@ -4927,11 +4964,7 @@ bnx2_close(struct net_device *dev)
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else
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reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
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bnx2_reset_chip(bp, reset_code);
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free_irq(bp->pdev->irq, dev);
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if (bp->flags & USING_MSI_FLAG) {
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pci_disable_msi(bp->pdev);
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bp->flags &= ~USING_MSI_FLAG;
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}
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bnx2_free_irq(bp);
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bnx2_free_skbs(bp);
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bnx2_free_mem(bp);
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bp->link_up = 0;
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@ -6095,6 +6128,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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}
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}
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if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
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if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
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bp->flags |= MSI_CAP_FLAG;
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}
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/* 5708 cannot support DMA addresses > 40-bit. */
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if (CHIP_NUM(bp) == CHIP_NUM_5708)
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persist_dma_mask = dma_mask = DMA_40BIT_MASK;
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@ -6468,12 +6468,14 @@ struct bnx2 {
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u32 last_status_idx;
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u32 flags;
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#define PCIX_FLAG 1
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#define PCI_32BIT_FLAG 2
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#define ONE_TDMA_FLAG 4 /* no longer used */
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#define NO_WOL_FLAG 8
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#define USING_MSI_FLAG 0x20
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#define ASF_ENABLE_FLAG 0x40
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#define PCIX_FLAG 0x00000001
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#define PCI_32BIT_FLAG 0x00000002
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#define ONE_TDMA_FLAG 0x00000004 /* no longer used */
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#define NO_WOL_FLAG 0x00000008
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#define USING_MSI_FLAG 0x00000020
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#define ASF_ENABLE_FLAG 0x00000040
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#define MSI_CAP_FLAG 0x00000080
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#define ONE_SHOT_MSI_FLAG 0x00000100
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/* Put tx producer and consumer fields in separate cache lines. */
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