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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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PCI: xgene: Add register accessors
Add device-specific register accessors for consistency across host drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
parent
4ecf6b0f83
commit
8e93c5132c
1 changed files with 44 additions and 42 deletions
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@ -76,6 +76,16 @@ struct xgene_pcie_port {
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u32 version;
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u32 version;
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};
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};
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static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
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{
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return readl(port->csr_base + reg);
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}
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static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
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{
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writel(val, port->csr_base + reg);
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}
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static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
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static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
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{
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{
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return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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@ -112,9 +122,9 @@ static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
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if (!pci_is_root_bus(bus))
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if (!pci_is_root_bus(bus))
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rtdid_val = (b << 8) | (d << 3) | f;
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rtdid_val = (b << 8) | (d << 3) | f;
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writel(rtdid_val, port->csr_base + RTDID);
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xgene_pcie_writel(port, RTDID, rtdid_val);
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/* read the register back to ensure flush */
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/* read the register back to ensure flush */
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readl(port->csr_base + RTDID);
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xgene_pcie_readl(port, RTDID);
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}
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}
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/*
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/*
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@ -182,26 +192,25 @@ static struct pci_ops xgene_pcie_ops = {
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static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
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static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
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u32 flags, u64 size)
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u32 flags, u64 size)
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{
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{
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void __iomem *csr_base = port->csr_base;
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u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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u32 val32 = 0;
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u32 val32 = 0;
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u32 val;
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u32 val;
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val32 = readl(csr_base + addr);
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val32 = xgene_pcie_readl(port, addr);
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val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
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val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
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writel(val, csr_base + addr);
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xgene_pcie_writel(port, addr, val);
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val32 = readl(csr_base + addr + 0x04);
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val32 = xgene_pcie_readl(port, addr + 0x04);
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val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
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val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
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writel(val, csr_base + addr + 0x04);
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xgene_pcie_writel(port, addr + 0x04, val);
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val32 = readl(csr_base + addr + 0x04);
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val32 = xgene_pcie_readl(port, addr + 0x04);
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val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
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val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
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writel(val, csr_base + addr + 0x04);
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xgene_pcie_writel(port, addr + 0x04, val);
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val32 = readl(csr_base + addr + 0x08);
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val32 = xgene_pcie_readl(port, addr + 0x08);
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val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
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val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
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writel(val, csr_base + addr + 0x08);
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xgene_pcie_writel(port, addr + 0x08, val);
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return mask;
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return mask;
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}
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}
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@ -209,15 +218,14 @@ static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
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static void xgene_pcie_linkup(struct xgene_pcie_port *port,
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static void xgene_pcie_linkup(struct xgene_pcie_port *port,
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u32 *lanes, u32 *speed)
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u32 *lanes, u32 *speed)
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{
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{
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void __iomem *csr_base = port->csr_base;
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u32 val32;
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u32 val32;
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port->link_up = false;
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port->link_up = false;
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val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
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val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
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if (val32 & LINK_UP_MASK) {
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if (val32 & LINK_UP_MASK) {
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port->link_up = true;
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port->link_up = true;
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*speed = PIPE_PHY_RATE_RD(val32);
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*speed = PIPE_PHY_RATE_RD(val32);
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val32 = readl(csr_base + BRIDGE_STATUS_0);
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val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
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*lanes = val32 >> 26;
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*lanes = val32 >> 26;
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}
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}
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}
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}
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@ -266,7 +274,6 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
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struct resource *res, u32 offset,
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struct resource *res, u32 offset,
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u64 cpu_addr, u64 pci_addr)
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u64 cpu_addr, u64 pci_addr)
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{
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{
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void __iomem *base = port->csr_base + offset;
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struct device *dev = port->dev;
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struct device *dev = port->dev;
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resource_size_t size = resource_size(res);
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resource_size_t size = resource_size(res);
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u64 restype = resource_type(res);
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u64 restype = resource_type(res);
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@ -287,22 +294,21 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
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dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
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dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
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(u64)size, min_size);
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(u64)size, min_size);
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writel(lower_32_bits(cpu_addr), base);
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xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
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writel(upper_32_bits(cpu_addr), base + 0x04);
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xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
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writel(lower_32_bits(mask), base + 0x08);
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xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
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writel(upper_32_bits(mask), base + 0x0c);
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xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
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writel(lower_32_bits(pci_addr), base + 0x10);
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xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
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writel(upper_32_bits(pci_addr), base + 0x14);
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xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
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}
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}
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static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
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static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
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{
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{
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void __iomem *csr_base = port->csr_base;
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u64 addr = port->cfg_addr;
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u64 addr = port->cfg_addr;
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writel(lower_32_bits(addr), csr_base + CFGBARL);
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xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
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writel(upper_32_bits(addr), csr_base + CFGBARH);
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xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
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writel(EN_REG, csr_base + CFGCTL);
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xgene_pcie_writel(port, CFGCTL, EN_REG);
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}
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}
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static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
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static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
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@ -353,12 +359,11 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
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static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
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static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
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u64 pim, u64 size)
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u64 pim, u64 size)
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{
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{
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void __iomem *addr = port->csr_base;
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xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
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xgene_pcie_writel(port, pim_reg + 0x04,
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writel(lower_32_bits(pim), addr + pim_reg);
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upper_32_bits(pim) | EN_COHERENCY);
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writel(upper_32_bits(pim) | EN_COHERENCY, addr + pim_reg + 0x04);
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xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
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writel(lower_32_bits(size), addr + pim_reg + 0x10);
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xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
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writel(upper_32_bits(size), addr + pim_reg + 0x14);
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}
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}
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/*
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/*
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@ -388,7 +393,6 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
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static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
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static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
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struct of_pci_range *range, u8 *ib_reg_mask)
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struct of_pci_range *range, u8 *ib_reg_mask)
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{
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{
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void __iomem *csr_base = port->csr_base;
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void __iomem *cfg_base = port->cfg_base;
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void __iomem *cfg_base = port->cfg_base;
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struct device *dev = port->dev;
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struct device *dev = port->dev;
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void *bar_addr;
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void *bar_addr;
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@ -420,17 +424,15 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
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pim_reg = PIM1_1L;
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pim_reg = PIM1_1L;
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break;
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break;
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case 1:
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case 1:
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bar_addr = csr_base + IBAR2;
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xgene_pcie_writel(port, IBAR2, bar_low);
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writel(bar_low, bar_addr);
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xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
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writel(lower_32_bits(mask), csr_base + IR2MSK);
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pim_reg = PIM2_1L;
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pim_reg = PIM2_1L;
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break;
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break;
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case 2:
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case 2:
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bar_addr = csr_base + IBAR3L;
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xgene_pcie_writel(port, IBAR3L, bar_low);
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writel(bar_low, bar_addr);
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xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
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writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
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xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
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writel(lower_32_bits(mask), csr_base + IR3MSKL);
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xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
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writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
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pim_reg = PIM3_1L;
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pim_reg = PIM3_1L;
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break;
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break;
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}
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}
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@ -486,7 +488,7 @@ static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
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int i;
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int i;
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for (i = PIM1_1L; i <= CFGCTL; i += 4)
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for (i = PIM1_1L; i <= CFGCTL; i += 4)
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writel(0x0, port->csr_base + i);
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xgene_pcie_writel(port, i, 0);
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}
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}
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static int xgene_pcie_setup(struct xgene_pcie_port *port,
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static int xgene_pcie_setup(struct xgene_pcie_port *port,
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@ -501,7 +503,7 @@ static int xgene_pcie_setup(struct xgene_pcie_port *port,
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/* setup the vendor and device IDs correctly */
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/* setup the vendor and device IDs correctly */
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val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
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val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
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writel(val, port->csr_base + BRIDGE_CFG_0);
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xgene_pcie_writel(port, BRIDGE_CFG_0, val);
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ret = xgene_pcie_map_ranges(port, res, io_base);
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ret = xgene_pcie_map_ranges(port, res, io_base);
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if (ret)
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if (ret)
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