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arm64: dts: renesas: r9a07g054: Fillup the ADC stub node

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Fillup the ADC stub node in RZ/V2L (R9A07G054) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220224125843.29733-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2022-02-24 12:58:43 +00:00 committed by Geert Uytterhoeven
parent 3123109284
commit 8eb5092e64
1 changed files with 38 additions and 1 deletions
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39
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
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@ -260,8 +260,45 @@ i2c3: i2c@10058c00 {
};
adc: adc@10059000 {
compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G054_ADC_PCLK>;
clock-names = "adclk", "pclk";
resets = <&cpg R9A07G054_ADC_PRESETN>,
<&cpg R9A07G054_ADC_ADRST_N>;
reset-names = "presetn", "adrst-n";
power-domains = <&cpg>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
channel@3 {
reg = <3>;
};
channel@4 {
reg = <4>;
};
channel@5 {
reg = <5>;
};
channel@6 {
reg = <6>;
};
channel@7 {
reg = <7>;
};
};
sbc: spi@10060000 {