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The i.MX cleanup for 4.8:

Browse source 
- A series from Arnd to clean up cpu_is_mx*() from i.MX platform
  - A series from Andrey to clean up i.MX L2-cache code by using
    core support as much as possible
  - Remove the orphan header eukrea-baseboards.h from i.MX platform
  - Remove boilerplate code from TZIC driver by using IRQCHIP_DECLARE
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Merge tag 'imx-cleanup-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/cleanup

The i.MX cleanup for 4.8:
 - A series from Arnd to clean up cpu_is_mx*() from i.MX platform
 - A series from Andrey to clean up i.MX L2-cache code by using
   core support as much as possible
 - Remove the orphan header eukrea-baseboards.h from i.MX platform
 - Remove boilerplate code from TZIC driver by using IRQCHIP_DECLARE

* tag 'imx-cleanup-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: remove cpu_is_mx*()
  ARM: imx: remove last call to cpu_is_mx5*
  ARM: imx: rework mx27_pm_init() call
  ARM: imx: deconstruct mx3_idle
  ARM: imx: deconstruct mxc_rnga initialization
  ARM: imx: remove cpu_is_mx1 check
  ARM: i.MX: Do not explicitly call l2x0_of_init()
  ARM: i.MX: system.c: Tweak prefetch settings for performance
  ARM: i.MX: system.c: Replace magic numbers
  ARM: i.MX: system.c: Remove redundant errata 752271 code
  ARM: i.MX: system.c: Convert goto to if statement
  ARM: imx: Use IRQCHIP_DECLARE for TZIC
  ARM: imx: Remove orphan header

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-07-05 20:57:57 -07:00
commit 8ec3dc29e6
25 changed files with 89 additions and 316 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/mach-imx/Kconfig
View file

@ -44,9 +44,6 @@ config MXC_USE_EPIT
uses the same clocks as the GPT. Anyway, on some systems the GPT
may be in use for other purposes.
config ARCH_HAS_RNGA
bool
config HAVE_IMX_ANATOP
bool
@ -90,7 +87,6 @@ config SOC_IMX27
config SOC_IMX31
bool
select CPU_V6
select IMX_HAVE_PLATFORM_MXC_RNGA
select MXC_AVIC
select SMP_ON_UP if SMP

4
arch/arm/mach-imx/Makefile
View file

@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o ehci-imx35.o pm-imx3.o
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o ehci-imx35.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)

3
arch/arm/mach-imx/common.h
View file

@ -32,7 +32,6 @@ void imx27_init_early(void);
void imx31_init_early(void);
void imx35_init_early(void);
void mxc_init_irq(void __iomem *);
void tzic_init_irq(void);
void mx1_init_irq(void);
void mx21_init_irq(void);
void mx27_init_irq(void);
@ -55,6 +54,7 @@ struct platform_device *mxc_register_gpio(char *name, int id,
void mxc_set_cpu_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *);
void mxc_arch_reset_init(void __iomem *);
void imx1_reset_init(void __iomem *);
void imx_set_aips(void __iomem *);
void imx_aips_allow_unprivileged_access(const char *compat);
int mxc_device_init(void);
@ -67,6 +67,7 @@ void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
void imx25_pm_init(void);
void imx27_pm_init(void);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */

8
arch/arm/mach-imx/cpu-imx5.c
View file

@ -60,13 +60,9 @@ static int get_mx51_srev(void)
/*
* Returns:
* the silicon revision of the cpu
* -EINVAL - not a mx51
*/
int mx51_revision(void)
{
if (!cpu_is_mx51())
return -EINVAL;
if (mx5_cpu_rev == -1)
mx5_cpu_rev = get_mx51_srev();
@ -112,13 +108,9 @@ static int get_mx53_srev(void)
/*
* Returns:
* the silicon revision of the cpu
* -EINVAL - not a mx53
*/
int mx53_revision(void)
{
if (!cpu_is_mx53())
return -EINVAL;
if (mx5_cpu_rev == -1)
mx5_cpu_rev = get_mx53_srev();

2
arch/arm/mach-imx/cpu.c
View file

@ -10,8 +10,6 @@
#include "common.h"
unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);
static unsigned int imx_soc_revision;
void mxc_set_cpu_type(unsigned int type)

4
arch/arm/mach-imx/devices/Kconfig
View file

@ -57,10 +57,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
config IMX_HAVE_PLATFORM_MXC_NAND
bool
config IMX_HAVE_PLATFORM_MXC_RNGA
bool
select ARCH_HAS_RNGA
config IMX_HAVE_PLATFORM_MXC_RTC
bool

53
arch/arm/mach-imx/devices/platform-mxc_rnga.c
View file

@ -1,53 +0,0 @@
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include "../hardware.h"
#include "devices-common.h"
struct imx_mxc_rnga_data {
resource_size_t iobase;
};
#define imx_mxc_rnga_data_entry_single(soc) \
{ \
.iobase = soc ## _RNGA_BASE_ADDR, \
}
#ifdef CONFIG_SOC_IMX31
static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
imx_mxc_rnga_data_entry_single(MX31);
#endif /* ifdef CONFIG_SOC_IMX31 */
static struct platform_device *__init imx_add_mxc_rnga(
const struct imx_mxc_rnga_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
return imx_add_platform_device("mxc_rnga", -1,
res, ARRAY_SIZE(res), NULL, 0);
}
static int __init imxXX_add_mxc_rnga(void)
{
struct platform_device *ret;
#if defined(CONFIG_SOC_IMX31)
if (cpu_is_mx31())
ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
else
#endif /* if defined(CONFIG_SOC_IMX31) */
ret = ERR_PTR(-ENODEV);
return PTR_ERR_OR_ZERO(ret);
}
arch_initcall(imxXX_add_mxc_rnga);

42
arch/arm/mach-imx/eukrea-baseboards.h
View file

@ -1,42 +0,0 @@
/*
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
*
* Based on board-pcm038.h which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_EUKREA_BASEBOARDS_H__
#define __MACH_EUKREA_BASEBOARDS_H__
#ifndef __ASSEMBLY__
/*
* This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls baseboard's init function.
* TODO: Add your own baseboard init function and call it from
* inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
*
* This example here is for the development board. Refer
* mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
* mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
*/
extern void eukrea_mbimxsd25_baseboard_init(void);
extern void eukrea_mbimxsd35_baseboard_init(void);
#endif
#endif /* __MACH_EUKREA_BASEBOARDS_H__ */

1
arch/arm/mach-imx/imx27-dt.c
View file

@ -27,5 +27,6 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.init_late = imx27_pm_init,
.dt_compat = imx27_dt_board_compat,
MACHINE_END

12
arch/arm/mach-imx/imx31-dt.c
View file

@ -28,10 +28,22 @@ static void __init imx31_dt_timer_init(void)
mx31_clocks_init_dt();
}
/* FIXME: replace with DT binding */
static const struct resource imx31_rnga_res[] __initconst = {
DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
};
static void __init imx31_dt_mach_init(void)
{
platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
ARRAY_SIZE(imx31_rnga_res));
}
DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.init_time = imx31_dt_timer_init,
.init_machine = imx31_dt_mach_init,
.dt_compat = imx31_dt_board_compat,
MACHINE_END

10
arch/arm/mach-imx/imx35-dt.c
View file

@ -20,20 +20,16 @@
#include "common.h"
#include "mx35.h"
static void __init imx35_irq_init(void)
{
imx_init_l2cache();
mx35_init_irq();
}
static const char * const imx35_dt_board_compat[] __initconst = {
"fsl,imx35",
NULL
};
DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = imx35_irq_init,
.init_irq = mx35_init_irq,
.dt_compat = imx35_dt_board_compat,
MACHINE_END

1
arch/arm/mach-imx/mach-imx50.c
View file

@ -22,6 +22,5 @@ static const char * const imx50_dt_board_compat[] __initconst = {
};
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
.init_irq = tzic_init_irq,
.dt_compat = imx50_dt_board_compat,
MACHINE_END

1
arch/arm/mach-imx/mach-imx51.c
View file

@ -69,7 +69,6 @@ static const char * const imx51_dt_board_compat[] __initconst = {
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
.init_early = imx51_init_early,
.init_irq = tzic_init_irq,
.init_machine = imx51_dt_init,
.init_late = imx51_init_late,
.dt_compat = imx51_dt_board_compat,

1
arch/arm/mach-imx/mach-imx53.c
View file

@ -49,7 +49,6 @@ static const char * const imx53_dt_board_compat[] __initconst = {
DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
.init_early = imx53_init_early,
.init_irq = tzic_init_irq,
.init_machine = imx53_dt_init,
.init_late = imx53_init_late,
.dt_compat = imx53_dt_board_compat,

2
arch/arm/mach-imx/mach-imx6q.c
View file

@ -407,6 +407,8 @@ static const char * const imx6q_dt_compat[] __initconst = {
};
DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.smp = smp_ops(imx_smp_ops),
.map_io = imx6q_map_io,
.init_irq = imx6q_init_irq,

2
arch/arm/mach-imx/mach-imx6sl.c
View file

@ -75,6 +75,8 @@ static const char * const imx6sl_dt_compat[] __initconst = {
};
DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_irq = imx6sl_init_irq,
.init_machine = imx6sl_init_machine,
.init_late = imx6sl_init_late,

2
arch/arm/mach-imx/mach-imx6sx.c
View file

@ -103,6 +103,8 @@ static const char * const imx6sx_dt_compat[] __initconst = {
};
DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_irq = imx6sx_init_irq,
.init_machine = imx6sx_init_machine,
.dt_compat = imx6sx_dt_compat,

2
arch/arm/mach-imx/mm-imx1.c
View file

@ -50,7 +50,7 @@ void __init mx1_init_irq(void)
void __init imx1_soc_init(void)
{
mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
mxc_device_init();
mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,

2
arch/arm/mach-imx/mm-imx27.c
View file

@ -98,4 +98,6 @@ void __init imx27_soc_init(void)
/* imx27 has the imx21 type audmux */
platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
ARRAY_SIZE(imx27_audmux_res));
imx27_pm_init();
}

32
arch/arm/mach-imx/mm-imx3.c
View file

@ -19,6 +19,7 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pinctrl/machine.h>
#include <asm/pgtable.h>
@ -38,8 +39,6 @@ static void imx3_idle(void)
{
unsigned long reg = 0;
mx3_cpu_lp_set(MX3_WAIT);
__asm__ __volatile__(
/* disable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
@ -135,11 +134,20 @@ void __init mx31_map_io(void)
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
static void imx31_idle(void)
{
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK;
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
imx3_idle();
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
arch_ioremap_caller = imx3_ioremap_caller;
arm_pm_idle = imx3_idle;
arm_pm_idle = imx31_idle;
mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
}
@ -167,6 +175,10 @@ static const struct resource imx31_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
};
static const struct resource imx31_rnga_res[] __initconst = {
DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
};
void __init imx31_soc_init(void)
{
int to_version = mx31_revision() >> 4;
@ -195,6 +207,8 @@ void __init imx31_soc_init(void)
platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
ARRAY_SIZE(imx31_audmux_res));
platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
ARRAY_SIZE(imx31_rnga_res));
}
#endif /* ifdef CONFIG_SOC_IMX31 */
@ -212,11 +226,21 @@ void __init mx35_map_io(void)
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
static void imx35_idle(void)
{
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK;
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
imx3_idle();
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
arm_pm_idle = imx3_idle;
arm_pm_idle = imx35_idle;
arch_ioremap_caller = imx3_ioremap_caller;
mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
}

101
arch/arm/mach-imx/mxc.h
View file

@ -45,105 +45,7 @@
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#endif
#ifdef CONFIG_SOC_IMX1
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX1
# endif
# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
#else
# define cpu_is_mx1() (0)
#endif
#ifdef CONFIG_SOC_IMX21
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX21
# endif
# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
#else
# define cpu_is_mx21() (0)
#endif
#ifdef CONFIG_SOC_IMX25
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX25
# endif
# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
#else
# define cpu_is_mx25() (0)
#endif
#ifdef CONFIG_SOC_IMX27
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX27
# endif
# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
#else
# define cpu_is_mx27() (0)
#endif
#ifdef CONFIG_SOC_IMX31
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX31
# endif
# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
#else
# define cpu_is_mx31() (0)
#endif
#ifdef CONFIG_SOC_IMX35
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX35
# endif
# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
#else
# define cpu_is_mx35() (0)
#endif
#ifdef CONFIG_SOC_IMX51
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX51
# endif
# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
#else
# define cpu_is_mx51() (0)
#endif
#ifdef CONFIG_SOC_IMX53
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX53
# endif
# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
#else
# define cpu_is_mx53() (0)
#endif
#ifndef __ASSEMBLY__
#ifdef CONFIG_SOC_IMX6SL
static inline bool cpu_is_imx6sl(void)
{
@ -190,9 +92,6 @@ int tzic_enable_wake(void);
extern struct cpu_op *(*get_cpu_op)(int *op);
#endif
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
#define imx_readl readl_relaxed
#define imx_readw readw_relaxed
#define imx_writel writel_relaxed

8
arch/arm/mach-imx/pm-imx27.c
View file

@ -37,13 +37,7 @@ static const struct platform_suspend_ops mx27_suspend_ops = {
.valid = suspend_valid_only_mem,
};
static int __init mx27_pm_init(void)
void __init imx27_pm_init(void)
{
if (!cpu_is_mx27())
return 0;
suspend_set_ops(&mx27_suspend_ops);
return 0;
}
device_initcall(mx27_pm_init);

38
arch/arm/mach-imx/pm-imx3.c
View file

@ -1,38 +0,0 @@
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/io.h>
#include "common.h"
#include "crmregs-imx3.h"
#include "devices/devices-common.h"
#include "hardware.h"
/*
* Set cpu low power mode before WFI instruction. This function is called
* mx3 because it can be used for mx31 and mx35.
* Currently only WAIT_MODE is supported.
*/
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
{
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK;
switch (mode) {
case MX3_WAIT:
if (cpu_is_mx35())
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
break;
default:
pr_err("Unknown cpu power mode: %d\n", mode);
return;
}
}

60
arch/arm/mach-imx/system.c
View file

@ -34,25 +34,19 @@
static void __iomem *wdog_base;
static struct clk *wdog_clk;
static int wcr_enable = (1 << 2);
/*
* Reset the system. It is called by machine_restart().
*/
void mxc_restart(enum reboot_mode mode, const char *cmd)
{
unsigned int wcr_enable;
if (!wdog_base)
goto reset_fallback;
if (!IS_ERR(wdog_clk))
clk_enable(wdog_clk);
if (cpu_is_mx1())
wcr_enable = (1 << 0);
else
wcr_enable = (1 << 2);
/* Assert SRS signal */
imx_writew(wcr_enable, wdog_base);
/*
@ -89,6 +83,14 @@ void __init mxc_arch_reset_init(void __iomem *base)
clk_prepare(wdog_clk);
}
#ifdef CONFIG_SOC_IMX1
void __init imx1_reset_init(void __iomem *base)
{
wcr_enable = (1 << 0);
mxc_arch_reset_init(base);
}
#endif
#ifdef CONFIG_CACHE_L2X0
void __init imx_init_l2cache(void)
{
@ -98,38 +100,28 @@ void __init imx_init_l2cache(void)
np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
if (!np)
goto out;
return;
l2x0_base = of_iomap(np, 0);
if (!l2x0_base) {
of_node_put(np);
goto out;
if (!l2x0_base)
goto put_node;
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
/* Configure the L2 PREFETCH and POWER registers */
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
L310_PREFETCH_CTRL_INSTR_PREFETCH |
L310_PREFETCH_CTRL_DATA_PREFETCH;
/* Set perfetch offset to improve performance */
val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
val |= 15;
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
}
if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
goto skip_if_enabled;
/* Configure the L2 PREFETCH and POWER registers */
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
val |= 0x70800000;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
* But according to ARM PL310 errata: 752271
* ID: 752271: Double linefill feature can cause data corruption
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
* Workaround: The only workaround to this erratum is to disable the
* double linefill feature. This is the default behavior.
*/
if (cpu_is_imx6q())
val &= ~(1 << 30 | 1 << 23);
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
skip_if_enabled:
iounmap(l2x0_base);
put_node:
of_node_put(np);
out:
l2x0_of_init(0, ~0);
}
#endif

10
arch/arm/mach-imx/tzic.c
View file

@ -9,12 +9,11 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
@ -153,13 +152,11 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init tzic_init_irq(void)
static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
{
struct device_node *np;
int irq_base;
int i;
np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
tzic_base = of_iomap(np, 0);
WARN_ON(!tzic_base);
@ -199,7 +196,10 @@ void __init tzic_init_irq(void)
#endif
pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
return 0;
}
IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
/**
* tzic_enable_wake() - enable wakeup interrupt