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SoCFPGA dts updates for v5.19
- dtschema fix SPI NOR node - correct dt-bindings doc for Altera gpio driver - add support for n6000 Agilex platform and dt-bindings documentation -----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAmKG0LsUHGRpbmd1eWVu QGtlcm5lbC5vcmcACgkQGZQEC4GjKPQx8BAAobw+3vYmzR6IkqygI1b2ZyE5qIxr oCt/8d5gVKXBwt9ZdUEwGGb2YlyUBQmZjW72SVT6Nzh3RG34IuPgHJmj6Hb5hjTJ ESqAmM0nX+Z+X5/94SQ9E6CieBfFXD00C6nINf319xzLMOcP0mtnRktzwEH83RdH 3Qsp2U4Ax7yUO5+13i4VLY8EjauD3P9+mJKJyC0IQRPoUJJk3oT9JU2eUiFhdWTh kIza7yuwvkIamRUvzfq1Mpg//xp8Wsh0QjrsvvUFnOgyuZpC5l1FxTUCYtFwiH4d FUgtpp7GC8+SJcfoHMRqDSa6Gy6nDz2kXqAEHFbSXbo4ZbdusTnGvofBUPuKMU/c YlMoFrb4VW/aaM3NKDxmhpb/f/+94zQldayGbK35Tt47JEVBIQQAqQjdYSFWjLI3 OdMwTLtQcZfHAdwYjnv+xktdUhnz9oT6zhLTEW5Gsr1DwyA32jLNzkyUgDqTwptj lv8pl7R0j8tMutApHHaRTaCL1MxRJ8pElslXnc2eijqmpOYJa/OE3fqXz6mfu8QL QzKWk3cVHjPb7+4146QykqSwxus1GUfdZJT18qYtgRtWU9b3GOn9VAGSI8XeJpb0 J4yBap5MT4RTs7ix5nqhPZjZ1o7A/GnUOGbzAa+b4PZwlG96y4BieUsI5NVasMzf +pfQbOMhPiY8e5c= =lT9o -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKUh5IACgkQmmx57+YA GNkvlhAAkDphJQguFDl1tiPAdfwJVHwYR+TfaBmRfixSzt7mJqIotey2DyAvwaSn EITcJcvfccvfPX9iJCfUUi3KTI4ZbayHviOWFHCALfm3ap+cH8nBNJMT7vBNovDf hzV12TQF36HQ/REPt/AljDJiiQlF417h5aq2cWLHA3i7ChhhFQ3+rYW/65uhJBZM n3fgznPiGeHL4SIgUpwlF5cn4y3p3Krq5qgo+LR77WhBaFLNo62UOCqRHZTazDE8 8wS6R03ebDdODVGc0/ZLBreZo4VESm2q14mZHBa5z1gqoKFaAI+5X7FPjGdx1jSc hAx0nDZvdF9se/gxc86wJGJurKNWL8JFLR3ObhbEnPiSesShI8+ntFm3y/0IZBb6 49Smc6EMDDQkb9ncsrthXmrt2L6YpUxtOJJHqgTHnJ2Yn4oYhBlx/cgnRugH7C1h N5V6YkMuMeYnLx0mAxXNk3TBNkJqO6oVmQTqWhwtCNJcNLox+ORGR0OCy0ljcXfL o/3FJPubep2LijaM4Oxlr/d41ILEsnrS9kh/N62qmKRA3GtnWRqkQsI6JDzFSdfN dWUDD1b9cuPn/aZA9V7sO7jFLED64EbpXtslcalpuPMclRwiDc9BKWk2welgSQVE ltocSgWawcP4TuAVqD6ZubZwApUMEvwlrswwGr42IBQGLlDIOQ8= =6Odl -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_updates_for_v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late SoCFPGA dts updates for v5.19 - dtschema fix SPI NOR node - correct dt-bindings doc for Altera gpio driver - add support for n6000 Agilex platform and dt-bindings documentation * tag 'socfpga_dts_updates_for_v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: intel: add device tree for n6000 dt-bindings: intel: add binding for Intel n6000 dt-bindings: soc: add bindings for Intel HPS Copy Engine dt-bindings: gpio: altera: correct interrupt-cells ARM: dts: socfpga: align SPI NOR node name with dtschema Link: https://lore.kernel.org/r/20220519232317.16079-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
8eecf1c992
9 changed files with 128 additions and 8 deletions
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@ -18,6 +18,7 @@ properties:
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items:
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- enum:
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- intel,n5x-socdk
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- intel,socfpga-agilex-n6000
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- intel,socfpga-agilex-socdk
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- const: intel,socfpga-agilex
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@ -9,8 +9,9 @@ Required properties:
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- The second cell is reserved and is currently unused.
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- gpio-controller : Marks the device node as a GPIO controller.
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- interrupt-controller: Mark the device node as an interrupt controller
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- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware.
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- #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
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- The first cell is the GPIO offset number within the GPIO controller.
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- The second cell is the interrupt trigger type and level flags.
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- interrupts: Specify the interrupt.
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- altr,interrupt-type: Specifies the interrupt trigger type the GPIO
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hardware is synthesized. This field is required if the Altera GPIO controller
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@ -38,6 +39,6 @@ gpio_altr: gpio@ff200000 {
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altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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@ -0,0 +1,51 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2022, Intel Corporation
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel HPS Copy Engine
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maintainers:
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- Matthew Gerlach <matthew.gerlach@linux.intel.com>
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description: |
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The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
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a bootable image from host memory to HPS DDR. Additionally, there is a
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register the HPS can use to indicate the state of booting the copied image as
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well as a keep-a-live indication to the host.
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properties:
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compatible:
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const: intel,hps-copy-engine
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'#dma-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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bus@80000000 {
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compatible = "simple-bus";
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reg = <0x80000000 0x60000000>,
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<0xf9000000 0x00100000>;
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reg-names = "axi_h2f", "axi_h2f_lw";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
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dma-controller@0 {
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compatible = "intel,hps-copy-engine";
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reg = <0x00000000 0x00000000 0x00001000>;
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#dma-cells = <1>;
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};
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};
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@ -9,7 +9,7 @@
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&qspi {
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status = "okay";
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flash0: n25q00@0 {
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,mt25qu02g", "jedec,spi-nor";
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@ -121,7 +121,7 @@ &mmc0 {
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&qspi {
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status = "okay";
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flash0: n25q00@0 {
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,mt25qu02g", "jedec,spi-nor";
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@ -113,7 +113,7 @@ &usb1 {
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&qspi {
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status = "okay";
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flash0: n25q512a@0 {
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q512a", "jedec,spi-nor";
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@ -221,7 +221,7 @@ at24@50 {
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&qspi {
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status = "okay";
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n25q128@0 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128", "jedec,spi-nor";
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@ -238,7 +238,7 @@ n25q128@0 {
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cdns,tslch-ns = <4>;
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};
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n25q00@1 {
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flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,mt25qu02g", "jedec,spi-nor";
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
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dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
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socfpga_agilex_socdk.dtb \
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socfpga_agilex_socdk_nand.dtb \
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socfpga_n5x_socdk.dtb
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dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
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66
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
Normal file
66
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
Normal file
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021-2022, Intel Corporation
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*/
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#include "socfpga_agilex.dtsi"
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/ {
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model = "SoCFPGA Agilex n6000";
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compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";
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aliases {
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serial0 = &uart1;
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serial1 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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soc {
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bus@80000000 {
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compatible = "simple-bus";
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reg = <0x80000000 0x60000000>,
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<0xf9000000 0x00100000>;
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reg-names = "axi_h2f", "axi_h2f_lw";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
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dma-controller@0 {
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compatible = "intel,hps-copy-engine";
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reg = <0x00000000 0x00000000 0x00001000>;
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#dma-cells = <1>;
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};
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};
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};
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};
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&osc1 {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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&fpga_mgr {
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status = "disabled";
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};
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