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clk: sunxi: mod1 clock should modify it's parent 

add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Andrea Venturi 2016-03-21 17:10:38 +01:00 committed by Maxime Ripard
parent 92a39d9043
commit 8f0767611a
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/sunxi/clk-a10-mod1.c
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@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node)
clk = clk_register_composite(NULL, clk_name, parents, i,
&mux->hw, &clk_mux_ops,
NULL, NULL,
&gate->hw, &clk_gate_ops, 0);
&gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
if (IS_ERR(clk))
goto err_free_gate;