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clk: sunxi: mod1 clock should modify it's parent
add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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1 changed files with 1 additions and 1 deletions
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@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node)
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clk = clk_register_composite(NULL, clk_name, parents, i,
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clk = clk_register_composite(NULL, clk_name, parents, i,
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&mux->hw, &clk_mux_ops,
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&mux->hw, &clk_mux_ops,
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NULL, NULL,
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NULL, NULL,
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&gate->hw, &clk_gate_ops, 0);
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&gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
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if (IS_ERR(clk))
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if (IS_ERR(clk))
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goto err_free_gate;
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goto err_free_gate;
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