MIPS: mobileye: Add EyeQ5 dtsi
Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov <stanislav.samsonov@intel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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7c8697ef03
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@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq
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subdir-$(CONFIG_MACH_LOONGSON64) += loongson
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subdir-$(CONFIG_SOC_VCOREIII) += mscc
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subdir-$(CONFIG_MIPS_MALTA) += mti
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subdir-$(CONFIG_MACH_EYEQ5) += mobileye
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subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
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subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
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subdir-$(CONFIG_MACH_PIC32) += pic32
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@ -0,0 +1,292 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Copyright 2023 Mobileye Vision Technologies Ltd.
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*/
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/ {
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/* Fixed clock */
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pll_cpu: pll-cpu {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1500000000>;
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};
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pll_vdi: pll-vdi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1280000000>;
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};
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pll_per: pll-per {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <2000000000>;
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};
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pll_ddr0: pll-ddr0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1857210000>;
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};
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pll_ddr1: pll-ddr1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1857210000>;
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};
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/* PLL_CPU derivatives */
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occ_cpu: occ-cpu {
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compatible = "fixed-factor-clock";
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clocks = <&pll_cpu>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
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compatible = "fixed-factor-clock";
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clocks = <&occ_cpu>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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cpc_clk: cpc-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core0_clk: core0-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core1_clk: core1-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core2_clk: core2-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core3_clk: core3-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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cm_clk: cm-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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mem_clk: mem-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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occ_isram: occ-isram {
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compatible = "fixed-factor-clock";
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clocks = <&pll_cpu>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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isram_clk: isram-clk { /* gate ClkRstGen_isram */
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compatible = "fixed-factor-clock";
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clocks = <&occ_isram>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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occ_dbu: occ-dbu {
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compatible = "fixed-factor-clock";
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clocks = <&pll_cpu>;
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#clock-cells = <0>;
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clock-div = <10>;
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clock-mult = <1>;
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};
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si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
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compatible = "fixed-factor-clock";
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clocks = <&occ_dbu>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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/* PLL_VDI derivatives */
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occ_vdi: occ-vdi {
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compatible = "fixed-factor-clock";
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clocks = <&pll_vdi>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
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compatible = "fixed-factor-clock";
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clocks = <&occ_vdi>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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occ_can_ser: occ-can-ser {
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compatible = "fixed-factor-clock";
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clocks = <&pll_vdi>;
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#clock-cells = <0>;
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clock-div = <16>;
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clock-mult = <1>;
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};
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can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
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compatible = "fixed-factor-clock";
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clocks = <&occ_can_ser>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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i2c_ser_clk: i2c-ser-clk {
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compatible = "fixed-factor-clock";
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clocks = <&pll_vdi>;
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#clock-cells = <0>;
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clock-div = <20>;
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clock-mult = <1>;
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};
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/* PLL_PER derivatives */
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occ_periph: occ-periph {
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compatible = "fixed-factor-clock";
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clocks = <&pll_per>;
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#clock-cells = <0>;
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clock-div = <16>;
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clock-mult = <1>;
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};
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periph_clk: periph-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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can_clk: can-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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spi_clk: spi-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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i2c_clk: i2c-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "i2c_clk";
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};
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timer_clk: timer-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "timer_clk";
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};
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gpio_clk: gpio-clk {
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compatible = "fixed-factor-clock";
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clocks = <&occ_periph>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "gpio_clk";
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};
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emmc_sys_clk: emmc-sys-clk {
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compatible = "fixed-factor-clock";
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clocks = <&pll_per>;
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#clock-cells = <0>;
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clock-div = <10>;
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clock-mult = <1>;
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clock-output-names = "emmc_sys_clk";
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};
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ccf_ctrl_clk: ccf-ctrl-clk {
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compatible = "fixed-factor-clock";
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clocks = <&pll_per>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "ccf_ctrl_clk";
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};
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occ_mjpeg_core: occ-mjpeg-core {
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compatible = "fixed-factor-clock";
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clocks = <&pll_per>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "occ_mjpeg_core";
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};
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hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
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compatible = "fixed-factor-clock";
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clocks = <&occ_mjpeg_core>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "hsm_clk";
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};
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mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
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compatible = "fixed-factor-clock";
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clocks = <&occ_mjpeg_core>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "mjpeg_core_clk";
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};
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fcmu_a_clk: fcmu-a-clk {
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compatible = "fixed-factor-clock";
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clocks = <&pll_per>;
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#clock-cells = <0>;
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clock-div = <20>;
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clock-mult = <1>;
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clock-output-names = "fcmu_a_clk";
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};
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occ_pci_sys: occ-pci-sys {
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compatible = "fixed-factor-clock";
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clocks = <&pll_per>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "occ_pci_sys";
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};
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pclk: pclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>; /* 250MHz */
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};
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tsu_clk: tsu-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>; /* 125MHz */
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};
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};
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@ -0,0 +1,124 @@
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// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright 2023 Mobileye Vision Technologies Ltd.
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*/
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include "eyeq5-fixed-clocks.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "img,i6500";
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reg = <0>;
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clocks = <&core0_clk>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* These reserved memory regions are also defined in bootmanager
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* for configuring inbound translation for BARS, don't change
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* these without syncing with bootmanager
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*/
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shmem0_reserved: shmem@804000000 {
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reg = <0x8 0x04000000 0x0 0x1000000>;
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};
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shmem1_reserved: shmem@805000000 {
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reg = <0x8 0x05000000 0x0 0x1000000>;
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};
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pci0_msi_reserved: pci0-msi@806000000 {
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reg = <0x8 0x06000000 0x0 0x100000>;
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};
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pci1_msi_reserved: pci1-msi@806100000 {
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reg = <0x8 0x06100000 0x0 0x100000>;
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};
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mini_coredump0_reserved: mini-coredump0@806200000 {
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reg = <0x8 0x06200000 0x0 0x100000>;
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};
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mhm_reserved_0: the-mhm-reserved-0@0 {
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reg = <0x8 0x00000000 0x0 0x0000800>;
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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cpu_intc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "simple-bus";
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uart0: serial@800000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x800000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>, <&occ_periph>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: serial@900000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x900000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>, <&occ_periph>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart2: serial@a00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0xa00000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>, <&occ_periph>;
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clock-names = "uartclk", "apb_pclk";
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};
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gic: interrupt-controller@140000 {
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compatible = "mti,gic";
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reg = <0x0 0x140000 0x0 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpu_intc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&core0_clk>;
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};
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};
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};
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};
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