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ata_piix: SATA 2port controller port map fix
This patch adds a port map for ICH9 and ICH8 SATA controllers that have only 2 ports available in that mode. Signed-off-by: Jason Gaston <jason.d.gaston@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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3957df6160
commit
8f73a68801
1 changed files with 30 additions and 5 deletions
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@ -130,6 +130,7 @@ enum {
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ich8_sata_ahci = 9,
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piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
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tolapai_sata_ahci = 11,
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ich9_2port_sata = 12,
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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@ -238,19 +239,19 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* SATA Controller 1 IDE (ICH8) */
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{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller 2 IDE (ICH8) */
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{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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/* Mobile SATA Controller IDE (ICH8M) */
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{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller IDE (ICH9) */
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{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller IDE (ICH9) */
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{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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/* SATA Controller IDE (ICH9) */
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{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller IDE (Tolapai) */
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@ -448,6 +449,18 @@ static const struct piix_map_db tolapai_map_db = {
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},
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};
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static const struct piix_map_db ich9_2port_map_db = {
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.mask = 0x3,
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.port_enable = 0x3,
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.map = {
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/* PM PS SM SS MAP */
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{ P0, NA, P1, NA }, /* 00b */
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{ RV, RV, RV, RV }, /* 01b */
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{ RV, RV, RV, RV }, /* 10b */
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{ RV, RV, RV, RV },
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},
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};
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static const struct piix_map_db *piix_map_db_table[] = {
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[ich5_sata] = &ich5_map_db,
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[ich6_sata] = &ich6_map_db,
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@ -455,6 +468,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
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[ich6m_sata_ahci] = &ich6m_map_db,
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[ich8_sata_ahci] = &ich8_map_db,
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[tolapai_sata_ahci] = &tolapai_map_db,
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[ich9_2port_sata] = &ich9_2port_map_db,
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};
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static struct ata_port_info piix_port_info[] = {
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@ -570,6 +584,17 @@ static struct ata_port_info piix_port_info[] = {
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.udma_mask = ATA_UDMA6,
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.port_ops = &piix_sata_ops,
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},
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[ich9_2port_sata] =
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{
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.sht = &piix_sht,
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = ATA_UDMA6,
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.port_ops = &piix_sata_ops,
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},
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};
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static struct pci_bits piix_enable_bits[] = {
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