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net: sxgbe: add Checksum offload support for Samsung sxgbe
This patch adds TX and RX checksum offload support. Signed-off-by: Vipul Pandya <vipul.pandya@samsung.com> Neatening-by: Joe Perches <joe@perches.com> Signed-off-by: Byungho An <bh74.an@samsung.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
1051125d8d
commit
8f7807ae41
4 changed files with 61 additions and 12 deletions
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@ -340,6 +340,10 @@ struct sxgbe_core_ops {
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void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
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const int tw);
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void (*set_eee_pls)(void __iomem *ioaddr, const int link);
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/* Enable disable checksum offload operations */
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void (*enable_rx_csum)(void __iomem *ioaddr);
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void (*disable_rx_csum)(void __iomem *ioaddr);
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};
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const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
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@ -452,6 +456,7 @@ struct sxgbe_priv_data {
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struct sxgbe_ops *hw; /* sxgbe specific ops */
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int no_csum_insertion;
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int irq;
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int rxcsum_insertion;
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spinlock_t stats_lock; /* lock for tx/rx statatics */
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struct phy_device *phydev;
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@ -218,6 +218,24 @@ static void sxgbe_set_eee_timer(void __iomem *ioaddr,
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writel(value, ioaddr + SXGBE_CORE_LPI_TIMER_CTRL);
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}
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static void sxgbe_enable_rx_csum(void __iomem *ioaddr)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE;
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writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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}
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static void sxgbe_disable_rx_csum(void __iomem *ioaddr)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE;
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writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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}
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const struct sxgbe_core_ops core_ops = {
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.core_init = sxgbe_core_init,
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.dump_regs = sxgbe_core_dump_regs,
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@ -234,6 +252,8 @@ const struct sxgbe_core_ops core_ops = {
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.reset_eee_mode = sxgbe_reset_eee_mode,
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.set_eee_timer = sxgbe_set_eee_timer,
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.set_eee_pls = sxgbe_set_eee_pls,
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.enable_rx_csum = sxgbe_enable_rx_csum,
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.disable_rx_csum = sxgbe_disable_rx_csum,
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};
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const struct sxgbe_core_ops *sxgbe_get_core_ops(void)
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@ -113,7 +113,7 @@ struct sxgbe_rx_norm_desc {
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/* WB RDES3 */
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u32 pkt_len:14;
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u32 rdes3_reserved:1;
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u32 err_summary:15;
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u32 err_summary:1;
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u32 err_l2_type:4;
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u32 layer34_pkt_type:4;
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u32 no_coagulation_pkt:1;
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@ -1252,6 +1252,7 @@ void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
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static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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unsigned int entry, frag_num;
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int cksum_flag = 0;
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struct netdev_queue *dev_txq;
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unsigned txq_index = skb_get_queue_mapping(skb);
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struct sxgbe_priv_data *priv = netdev_priv(dev);
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@ -1332,7 +1333,7 @@ static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
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__func__);
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priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
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no_pagedlen, 0);
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no_pagedlen, cksum_flag);
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}
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}
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@ -1350,7 +1351,7 @@ static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
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/* prepare the descriptor */
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priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
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len, 0);
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len, cksum_flag);
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/* memory barrier to flush descriptor */
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wmb();
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@ -1471,6 +1472,8 @@ static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
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unsigned int entry = priv->rxq[qnum]->cur_rx;
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unsigned int next_entry = 0;
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unsigned int count = 0;
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int checksum;
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int status;
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while (count < limit) {
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struct sxgbe_rx_norm_desc *p;
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@ -1487,7 +1490,18 @@ static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
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next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
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prefetch(priv->rxq[qnum]->dma_rx + next_entry);
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/*TO DO read the status of the incoming frame */
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/* Read the status of the incoming frame and also get checksum
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* value based on whether it is enabled in SXGBE hardware or
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* not.
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*/
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status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
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&checksum);
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if (unlikely(status < 0)) {
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entry = next_entry;
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continue;
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}
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if (unlikely(!priv->rxcsum_insertion))
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checksum = CHECKSUM_NONE;
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skb = priv->rxq[qnum]->rx_skbuff[entry];
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@ -1501,7 +1515,11 @@ static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
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skb_put(skb, frame_len);
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netif_receive_skb(skb);
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skb->ip_summed = checksum;
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if (checksum == CHECKSUM_NONE)
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netif_receive_skb(skb);
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else
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napi_gro_receive(&priv->napi, skb);
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entry = next_entry;
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}
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@ -1748,15 +1766,15 @@ static int sxgbe_set_features(struct net_device *dev,
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{
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struct sxgbe_priv_data *priv = netdev_priv(dev);
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netdev_features_t changed = dev->features ^ features;
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u32 ctrl;
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if (changed & NETIF_F_RXCSUM) {
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ctrl = readl(priv->ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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if (features & NETIF_F_RXCSUM)
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ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE;
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else
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ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE;
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writel(ctrl, priv->ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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if (features & NETIF_F_RXCSUM) {
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priv->hw->mac->enable_rx_csum(priv->ioaddr);
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priv->rxcsum_insertion = true;
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} else {
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priv->hw->mac->disable_rx_csum(priv->ioaddr);
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priv->rxcsum_insertion = false;
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}
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}
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return 0;
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@ -2115,6 +2133,12 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
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}
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}
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/* Enable Rx checksum offload */
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if (priv->hw_cap.rx_csum_offload) {
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priv->hw->mac->enable_rx_csum(priv->ioaddr);
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priv->rxcsum_insertion = true;
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}
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/* Rx Watchdog is available, enable depend on platform data */
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if (!priv->plat->riwt_off) {
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priv->use_riwt = 1;
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