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Merge branch 'sh_eth-get-rid-of-the-dedicated-regiseter-mapping-for-RZ-A1-R7S72100'
Sergei Shtylyov says: ==================== sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Here's a set of 5 patches against DaveM's 'net-next.git' repo. I changed my mind about the RZ/A1 SoC needing its own register map -- now that we don't depend on the register map array in order to determine whether a given register exists any more, we can add a new flag to determine if the GECMR exists (this register is present only on true GEther chips, not RZ/A1). We also need to add the sh_eth_cpu_data::* flag checks where they were missing so far: in the ethtool API for the register dump. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
8fb9df9775
2 changed files with 29 additions and 77 deletions
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@ -142,69 +142,6 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[FWALCR1] = 0x00b4,
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[FWALCR1] = 0x00b4,
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};
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};
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static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
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SH_ETH_OFFSET_DEFAULTS,
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[CSMR] = 0x04E4,
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[ECMR] = 0x0500,
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[RFLR] = 0x0508,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[MAFCR] = 0x0778,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWSLC] = 0x0038,
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[TSU_VTAG0] = 0x0058,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TSU_ADRH0] = 0x0100,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008C,
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};
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static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
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static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
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SH_ETH_OFFSET_DEFAULTS,
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SH_ETH_OFFSET_DEFAULTS,
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@ -569,6 +506,9 @@ static void sh_eth_set_rate_gether(struct net_device *ndev)
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{
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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struct sh_eth_private *mdp = netdev_priv(ndev);
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if (WARN_ON(!mdp->cd->gecmr))
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return;
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switch (mdp->speed) {
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switch (mdp->speed) {
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case 10: /* 10BASE */
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case 10: /* 10BASE */
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sh_eth_write(ndev, GECMR_10, GECMR);
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sh_eth_write(ndev, GECMR_10, GECMR);
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@ -590,7 +530,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
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.chip_reset = sh_eth_chip_reset,
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.chip_reset = sh_eth_chip_reset,
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.set_duplex = sh_eth_set_duplex,
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.set_duplex = sh_eth_set_duplex,
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.register_type = SH_ETH_REG_FAST_RZ,
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.register_type = SH_ETH_REG_GIGABIT,
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.edtrr_trns = EDTRR_TRNS_GETHER,
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.edtrr_trns = EDTRR_TRNS_GETHER,
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.ecsr_value = ECSR_ICD,
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.ecsr_value = ECSR_ICD,
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@ -663,6 +603,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.apr = 1,
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.apr = 1,
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.mpr = 1,
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.mpr = 1,
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.tpauser = 1,
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.tpauser = 1,
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.gecmr = 1,
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.bculr = 1,
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.bculr = 1,
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.hw_swap = 1,
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.hw_swap = 1,
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.rpadir = 1,
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.rpadir = 1,
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@ -788,6 +729,7 @@ static struct sh_eth_cpu_data r8a77980_data = {
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.apr = 1,
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.apr = 1,
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.mpr = 1,
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.mpr = 1,
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.tpauser = 1,
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.tpauser = 1,
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.gecmr = 1,
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.bculr = 1,
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.bculr = 1,
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.hw_swap = 1,
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.hw_swap = 1,
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.nbst = 1,
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.nbst = 1,
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@ -957,6 +899,9 @@ static void sh_eth_set_rate_giga(struct net_device *ndev)
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{
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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struct sh_eth_private *mdp = netdev_priv(ndev);
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if (WARN_ON(!mdp->cd->gecmr))
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return;
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switch (mdp->speed) {
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switch (mdp->speed) {
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case 10: /* 10BASE */
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case 10: /* 10BASE */
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sh_eth_write(ndev, 0x00000000, GECMR);
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sh_eth_write(ndev, 0x00000000, GECMR);
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@ -1002,6 +947,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
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.apr = 1,
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.apr = 1,
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.mpr = 1,
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.mpr = 1,
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.tpauser = 1,
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.tpauser = 1,
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.gecmr = 1,
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.bculr = 1,
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.bculr = 1,
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.hw_swap = 1,
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.hw_swap = 1,
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.rpadir = 1,
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.rpadir = 1,
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@ -1042,6 +988,7 @@ static struct sh_eth_cpu_data sh7734_data = {
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.apr = 1,
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.apr = 1,
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.mpr = 1,
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.mpr = 1,
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.tpauser = 1,
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.tpauser = 1,
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.gecmr = 1,
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.bculr = 1,
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.bculr = 1,
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.hw_swap = 1,
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.hw_swap = 1,
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.no_trimd = 1,
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.no_trimd = 1,
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@ -1083,6 +1030,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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.apr = 1,
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.apr = 1,
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.mpr = 1,
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.mpr = 1,
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.tpauser = 1,
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.tpauser = 1,
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.gecmr = 1,
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.bculr = 1,
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.bculr = 1,
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.hw_swap = 1,
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.hw_swap = 1,
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.no_trimd = 1,
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.no_trimd = 1,
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@ -2140,10 +2088,12 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
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add_reg(EESR);
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add_reg(EESR);
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add_reg(EESIPR);
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add_reg(EESIPR);
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add_reg(TDLAR);
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add_reg(TDLAR);
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if (!cd->no_xdfar)
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add_reg(TDFAR);
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add_reg(TDFAR);
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add_reg(TDFXR);
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add_reg(TDFXR);
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add_reg(TDFFR);
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add_reg(TDFFR);
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add_reg(RDLAR);
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add_reg(RDLAR);
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if (!cd->no_xdfar)
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add_reg(RDFAR);
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add_reg(RDFAR);
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add_reg(RDFXR);
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add_reg(RDFXR);
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add_reg(RDFFR);
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add_reg(RDFFR);
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@ -2179,21 +2129,26 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
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if (cd->tpauser)
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if (cd->tpauser)
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add_reg(TPAUSER);
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add_reg(TPAUSER);
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add_reg(TPAUSECR);
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add_reg(TPAUSECR);
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if (cd->gecmr)
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add_reg(GECMR);
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add_reg(GECMR);
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if (cd->bculr)
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if (cd->bculr)
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add_reg(BCULR);
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add_reg(BCULR);
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add_reg(MAHR);
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add_reg(MAHR);
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add_reg(MALR);
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add_reg(MALR);
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if (!cd->no_tx_cntrs) {
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add_reg(TROCR);
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add_reg(TROCR);
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add_reg(CDCR);
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add_reg(CDCR);
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add_reg(LCCR);
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add_reg(LCCR);
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add_reg(CNDCR);
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add_reg(CNDCR);
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}
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add_reg(CEFCR);
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add_reg(CEFCR);
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add_reg(FRECR);
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add_reg(FRECR);
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add_reg(TSFRCR);
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add_reg(TSFRCR);
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add_reg(TLFRCR);
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add_reg(TLFRCR);
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if (cd->cexcr) {
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add_reg(CERCR);
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add_reg(CERCR);
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add_reg(CEECR);
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add_reg(CEECR);
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}
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add_reg(MAFCR);
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add_reg(MAFCR);
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if (cd->rtrate)
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if (cd->rtrate)
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add_reg(RTRATE);
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add_reg(RTRATE);
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@ -3121,9 +3076,6 @@ static const u16 *sh_eth_get_register_offset(int register_type)
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case SH_ETH_REG_GIGABIT:
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case SH_ETH_REG_GIGABIT:
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reg_offset = sh_eth_offset_gigabit;
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reg_offset = sh_eth_offset_gigabit;
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break;
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break;
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case SH_ETH_REG_FAST_RZ:
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reg_offset = sh_eth_offset_fast_rz;
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break;
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case SH_ETH_REG_FAST_RCAR:
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case SH_ETH_REG_FAST_RCAR:
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reg_offset = sh_eth_offset_fast_rcar;
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reg_offset = sh_eth_offset_fast_rcar;
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break;
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break;
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@ -145,7 +145,6 @@ enum {
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enum {
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enum {
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SH_ETH_REG_GIGABIT,
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SH_ETH_REG_GIGABIT,
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SH_ETH_REG_FAST_RZ,
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SH_ETH_REG_FAST_RCAR,
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SH_ETH_REG_FAST_RCAR,
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SH_ETH_REG_FAST_SH4,
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SH_ETH_REG_FAST_SH4,
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SH_ETH_REG_FAST_SH3_SH2
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SH_ETH_REG_FAST_SH3_SH2
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@ -490,6 +489,7 @@ struct sh_eth_cpu_data {
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unsigned apr:1; /* EtherC has APR */
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unsigned apr:1; /* EtherC has APR */
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unsigned mpr:1; /* EtherC has MPR */
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unsigned mpr:1; /* EtherC has MPR */
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unsigned tpauser:1; /* EtherC has TPAUSER */
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unsigned tpauser:1; /* EtherC has TPAUSER */
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unsigned gecmr:1; /* EtherC has GECMR */
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unsigned bculr:1; /* EtherC has BCULR */
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unsigned bculr:1; /* EtherC has BCULR */
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unsigned tsu:1; /* EtherC has TSU */
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unsigned tsu:1; /* EtherC has TSU */
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unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */
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unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */
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