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drm/amdgpu:fix world switch hang
for SR-IOV, we must keep the pipeline-sync in the protection of COND_EXEC, otherwise the command consumed by CPG is not consistent when world switch triggerd, e.g.: world switch hit and the IB frame is skipped so the fence won't signal, thus CP will jump to the next DMAframe's pipeline-sync command, and it will make CP hang foever. after pipelin-sync moved into COND_EXEC the consistency can be guaranteed Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bdb8cd10b9
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8fdf074f18
3 changed files with 9 additions and 5 deletions
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@ -130,6 +130,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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unsigned i;
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int r = 0;
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bool need_pipe_sync = false;
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if (num_ibs == 0)
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return -EINVAL;
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@ -165,7 +166,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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if (ring->funcs->emit_pipeline_sync && job &&
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((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
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amdgpu_vm_need_pipeline_sync(ring, job))) {
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amdgpu_ring_emit_pipeline_sync(ring);
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need_pipe_sync = true;
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dma_fence_put(tmp);
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}
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@ -173,7 +174,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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ring->funcs->insert_start(ring);
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if (job) {
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r = amdgpu_vm_flush(ring, job);
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r = amdgpu_vm_flush(ring, job, need_pipe_sync);
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if (r) {
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amdgpu_ring_undo(ring);
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return r;
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@ -743,7 +743,7 @@ static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
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*
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* Emit a VM flush when it is necessary.
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*/
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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@ -765,12 +765,15 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
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vm_flush_needed = true;
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}
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if (!vm_flush_needed && !gds_switch_needed)
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if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
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return 0;
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if (ring->funcs->init_cond_exec)
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patch_offset = amdgpu_ring_init_cond_exec(ring);
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if (need_pipe_sync)
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amdgpu_ring_emit_pipeline_sync(ring);
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if (ring->funcs->emit_vm_flush && vm_flush_needed) {
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struct dma_fence *fence;
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@ -222,7 +222,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_sync *sync, struct dma_fence *fence,
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struct amdgpu_job *job);
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
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void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
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unsigned vmid);
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void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
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