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spi/bfin_spi: use the SPI namespaced bit names
This lets us push the short SPI MMR bit names out of the global namespace. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
parent
2a045131db
commit
90008a641d
1 changed files with 11 additions and 10 deletions
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@ -504,8 +504,8 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
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* register until it goes low for 2 successive reads
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*/
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if (drv_data->tx != NULL) {
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while ((read_STAT(drv_data) & TXS) ||
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(read_STAT(drv_data) & TXS))
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while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
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(read_STAT(drv_data) & BIT_STAT_TXS))
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cpu_relax();
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}
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@ -514,14 +514,14 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
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dmastat, read_STAT(drv_data));
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timeout = jiffies + HZ;
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while (!(read_STAT(drv_data) & SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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if (!time_before(jiffies, timeout)) {
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dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
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break;
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} else
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cpu_relax();
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if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
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if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
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msg->state = ERROR_STATE;
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dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
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} else {
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@ -1000,11 +1000,12 @@ static int bfin_spi_setup(struct spi_device *spi)
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if (chip_info) {
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/* Make sure people stop trying to set fields via ctl_reg
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* when they should actually be using common SPI framework.
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* Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
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* Currently we let through: WOM EMISO PSSE GM SZ.
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* Not sure if a user actually needs/uses any of these,
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* but let's assume (for now) they do.
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*/
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if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
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if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \
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BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) {
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dev_err(&spi->dev, "do not set bits in ctl_reg "
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"that the SPI framework manages\n");
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goto error;
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@ -1022,13 +1023,13 @@ static int bfin_spi_setup(struct spi_device *spi)
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/* translate common spi framework into our register */
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if (spi->mode & SPI_CPOL)
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chip->ctl_reg |= CPOL;
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chip->ctl_reg |= BIT_CTL_CPOL;
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if (spi->mode & SPI_CPHA)
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chip->ctl_reg |= CPHA;
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chip->ctl_reg |= BIT_CTL_CPHA;
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if (spi->mode & SPI_LSB_FIRST)
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chip->ctl_reg |= LSBF;
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chip->ctl_reg |= BIT_CTL_LSBF;
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/* we dont support running in slave mode (yet?) */
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chip->ctl_reg |= MSTR;
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chip->ctl_reg |= BIT_CTL_MASTER;
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/*
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* Notice: for blackfin, the speed_hz is the value of register
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