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AMD IOMMU: add event handling code
This patch adds code for polling and printing out events generated by the AMD IOMMU. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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a80dc3e0e0
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90008ee4b8
3 changed files with 108 additions and 2 deletions
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@ -55,9 +55,94 @@ static int iommu_has_npcache(struct amd_iommu *iommu)
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*
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****************************************************************************/
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static void iommu_print_event(void *__evt)
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{
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u32 *event = __evt;
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int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
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int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
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int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
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int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
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u64 address = (u64)(((u64)event[3]) << 32) | event[2];
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printk(KERN_ERR "AMD IOMMU: Event logged [");
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switch (type) {
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case EVENT_TYPE_ILL_DEV:
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printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
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"address=0x%016llx flags=0x%04x]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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address, flags);
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break;
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case EVENT_TYPE_IO_FAULT:
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printk("IO_PAGE_FAULT device=%02x:%02x.%x "
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"domain=0x%04x address=0x%016llx flags=0x%04x]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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domid, address, flags);
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break;
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case EVENT_TYPE_DEV_TAB_ERR:
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printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
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"address=0x%016llx flags=0x%04x]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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address, flags);
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break;
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case EVENT_TYPE_PAGE_TAB_ERR:
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printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
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"domain=0x%04x address=0x%016llx flags=0x%04x]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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domid, address, flags);
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break;
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case EVENT_TYPE_ILL_CMD:
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printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
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break;
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case EVENT_TYPE_CMD_HARD_ERR:
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printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
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"flags=0x%04x]\n", address, flags);
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break;
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case EVENT_TYPE_IOTLB_INV_TO:
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printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
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"address=0x%016llx]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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address);
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break;
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case EVENT_TYPE_INV_DEV_REQ:
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printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
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"address=0x%016llx flags=0x%04x]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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address, flags);
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break;
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default:
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printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
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}
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}
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static void iommu_poll_events(struct amd_iommu *iommu)
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{
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u32 head, tail;
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unsigned long flags;
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spin_lock_irqsave(&iommu->lock, flags);
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head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
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tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
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while (head != tail) {
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iommu_print_event(iommu->evt_buf + head);
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head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
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}
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writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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irqreturn_t amd_iommu_int_handler(int irq, void *data)
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{
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return IRQ_NONE;
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struct amd_iommu *iommu;
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list_for_each_entry(iommu, &amd_iommu_list, list)
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iommu_poll_events(iommu);
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return IRQ_HANDLED;
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}
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/****************************************************************************
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@ -32,7 +32,6 @@
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/*
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* definitions for the ACPI scanning code
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*/
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#define PCI_BUS(x) (((x) >> 8) & 0xff)
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#define IVRS_HEADER_LENGTH 48
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#define ACPI_IVHD_TYPE 0x10
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@ -71,6 +71,25 @@
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/* MMIO status bits */
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#define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
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/* event logging constants */
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#define EVENT_ENTRY_SIZE 0x10
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#define EVENT_TYPE_SHIFT 28
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#define EVENT_TYPE_MASK 0xf
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#define EVENT_TYPE_ILL_DEV 0x1
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#define EVENT_TYPE_IO_FAULT 0x2
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#define EVENT_TYPE_DEV_TAB_ERR 0x3
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#define EVENT_TYPE_PAGE_TAB_ERR 0x4
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#define EVENT_TYPE_ILL_CMD 0x5
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#define EVENT_TYPE_CMD_HARD_ERR 0x6
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#define EVENT_TYPE_IOTLB_INV_TO 0x7
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#define EVENT_TYPE_INV_DEV_REQ 0x8
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#define EVENT_DEVID_MASK 0xffff
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#define EVENT_DEVID_SHIFT 0
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#define EVENT_DOMID_MASK 0xffff
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#define EVENT_DOMID_SHIFT 0
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#define EVENT_FLAGS_MASK 0xfff
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#define EVENT_FLAGS_SHIFT 0x10
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/* feature control bits */
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#define CONTROL_IOMMU_EN 0x00ULL
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#define CONTROL_HT_TUN_EN 0x01ULL
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@ -165,6 +184,9 @@
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#define MAX_DOMAIN_ID 65536
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/* FIXME: move this macro to <linux/pci.h> */
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#define PCI_BUS(x) (((x) >> 8) & 0xff)
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/*
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* This structure contains generic data for IOMMU protection domains
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* independent of their use.
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