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drm/i915/gt: Tidy up full-ppgtt on Ivybridge
With a couple more memory barriers dotted around the place we can significantly reduce the MTBF on Ivybridge. Still doesn't really help Haswell though. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191216142409.2605211-1-chris@chris-wilson.co.uk
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0a9a5532d2
commit
902eb748e5
2 changed files with 45 additions and 71 deletions
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@ -362,6 +362,12 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
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*/
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*/
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flags |= PIPE_CONTROL_CS_STALL;
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flags |= PIPE_CONTROL_CS_STALL;
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/*
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* CS_STALL suggests at least a post-sync write.
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*/
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flags |= PIPE_CONTROL_QW_WRITE;
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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/* Just flush everything. Experiments have shown that reducing the
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/* Just flush everything. Experiments have shown that reducing the
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* number of bits based on the write domains has little performance
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* number of bits based on the write domains has little performance
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* impact.
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* impact.
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@ -380,13 +386,6 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
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flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
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/*
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* TLB invalidate requires a post-sync write.
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*/
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flags |= PIPE_CONTROL_QW_WRITE;
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
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/* Workaround: we must issue a pipe_control with CS-stall bit
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/* Workaround: we must issue a pipe_control with CS-stall bit
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* set before a pipe_control command that has the state cache
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* set before a pipe_control command that has the state cache
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@ -1371,50 +1370,26 @@ static int load_pd_dir(struct i915_request *rq,
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const struct intel_engine_cs * const engine = rq->engine;
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const struct intel_engine_cs * const engine = rq->engine;
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u32 *cs;
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u32 *cs;
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cs = intel_ring_begin(rq, 12);
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cs = intel_ring_begin(rq, 10);
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if (IS_ERR(cs))
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = MI_LOAD_REGISTER_IMM(3);
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
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*cs++ = valid;
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*cs++ = valid;
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
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*cs++ = intel_gt_scratch_offset(rq->engine->gt,
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INTEL_GT_SCRATCH_FIELD_DEFAULT);
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
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*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
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*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
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*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
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*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
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/* Stall until the page table load is complete? */
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/* Stall until the page table load is complete? */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
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*cs++ = intel_gt_scratch_offset(rq->engine->gt,
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*cs++ = intel_gt_scratch_offset(engine->gt,
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INTEL_GT_SCRATCH_FIELD_DEFAULT);
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INTEL_GT_SCRATCH_FIELD_DEFAULT);
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intel_ring_advance(rq, cs);
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intel_ring_advance(rq, cs);
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return rq->engine->emit_flush(rq, EMIT_FLUSH);
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}
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static int flush_tlb(struct i915_request *rq)
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{
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const struct intel_engine_cs * const engine = rq->engine;
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u32 *cs;
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
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*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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return 0;
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return 0;
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}
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}
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@ -1590,16 +1565,17 @@ static int remap_l3(struct i915_request *rq)
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return 0;
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return 0;
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}
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}
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static int switch_context(struct i915_request *rq)
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static int switch_mm(struct i915_request *rq, struct i915_address_space *vm)
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{
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{
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struct intel_context *ce = rq->hw_context;
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struct i915_address_space *vm = vm_alias(ce);
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u32 hw_flags = 0;
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int ret;
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int ret;
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GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
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if (!vm)
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return 0;
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ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
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if (ret)
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return ret;
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if (vm) {
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/*
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/*
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* Not only do we need a full barrier (post-sync write) after
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* Not only do we need a full barrier (post-sync write) after
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* invalidating the TLBs, but we need to wait a little bit
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* invalidating the TLBs, but we need to wait a little bit
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@ -1608,34 +1584,30 @@ static int switch_context(struct i915_request *rq)
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* post-sync op, this extra pass appears vital before a
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* post-sync op, this extra pass appears vital before a
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* mm switch!
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* mm switch!
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*/
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*/
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ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
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if (ret)
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return ret;
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ret = flush_tlb(rq);
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if (ret)
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return ret;
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ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm), 0);
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if (ret)
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return ret;
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ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm), PP_DIR_DCLV_2G);
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ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm), PP_DIR_DCLV_2G);
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if (ret)
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if (ret)
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return ret;
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return ret;
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ret = flush_tlb(rq);
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return rq->engine->emit_flush(rq, EMIT_FLUSH);
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if (ret)
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return ret;
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ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
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if (ret)
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return ret;
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}
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}
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static int switch_context(struct i915_request *rq)
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{
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struct intel_context *ce = rq->hw_context;
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int ret;
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GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
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ret = switch_mm(rq, vm_alias(ce));
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if (ret)
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return ret;
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if (ce->state) {
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if (ce->state) {
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u32 hw_flags;
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GEM_BUG_ON(rq->engine->id != RCS0);
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GEM_BUG_ON(rq->engine->id != RCS0);
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hw_flags = 0;
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if (!test_bit(CONTEXT_VALID_BIT, &ce->flags))
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if (!test_bit(CONTEXT_VALID_BIT, &ce->flags))
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hw_flags = MI_RESTORE_INHIBIT;
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hw_flags = MI_RESTORE_INHIBIT;
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@ -1709,8 +1709,10 @@ static void gen6_flush_pd(struct gen6_ppgtt *ppgtt, u64 start, u64 end)
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gen6_for_each_pde(pt, pd, start, end, pde)
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gen6_for_each_pde(pt, pd, start, end, pde)
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gen6_write_pde(ppgtt, pde, pt);
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gen6_write_pde(ppgtt, pde, pt);
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mb();
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ioread32(ppgtt->pd_addr + pde - 1);
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ioread32(ppgtt->pd_addr + pde - 1);
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gen6_ggtt_invalidate(ppgtt->base.vm.gt->ggtt);
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gen6_ggtt_invalidate(ppgtt->base.vm.gt->ggtt);
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mb();
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mutex_unlock(&ppgtt->flush);
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mutex_unlock(&ppgtt->flush);
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}
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}
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