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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-25 02:09:42 +00:00
drm/rcar-du: Add internal LVDS encoder support
The R8A7790 includes two internal LVDS encoders. Support them in the DU driver. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
parent
7cbc05cb51
commit
90374b5c25
12 changed files with 374 additions and 3 deletions
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@ -7,3 +7,10 @@ config DRM_RCAR_DU
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help
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Choose this option if you have an R-Car chipset.
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If M is selected the module will be called rcar-du-drm.
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config DRM_RCAR_LVDS
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bool "R-Car DU LVDS Encoder Support"
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depends on DRM_RCAR_DU
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help
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Enable support the R-Car Display Unit embedded LVDS encoders
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(currently only on R8A7790).
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@ -7,4 +7,6 @@ rcar-du-drm-y := rcar_du_crtc.o \
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rcar_du_plane.o \
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rcar_du_vgacon.o
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obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
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rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_lvdsenc.o
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obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
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@ -26,8 +26,6 @@
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#include "rcar_du_plane.h"
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#include "rcar_du_regs.h"
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#define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc)
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static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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@ -39,6 +39,8 @@ struct rcar_du_crtc {
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struct rcar_du_plane *plane;
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};
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#define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc)
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int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index);
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void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable);
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void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
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@ -232,6 +232,7 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
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.encoder_type = DRM_MODE_ENCODER_NONE,
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},
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},
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.num_lvds = 0,
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};
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static const struct rcar_du_device_info rcar_du_r8a7790_info = {
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@ -255,6 +256,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
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.encoder_type = DRM_MODE_ENCODER_LVDS,
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},
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},
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.num_lvds = 2,
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};
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static const struct platform_device_id rcar_du_id_table[] = {
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@ -24,6 +24,7 @@ struct clk;
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struct device;
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struct drm_device;
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struct rcar_du_device;
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struct rcar_du_lvdsenc;
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#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK (1 << 0) /* Per-CRTC IRQ and clock */
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#define RCAR_DU_FEATURE_ALIGN_128B (1 << 1) /* Align pitches to 128 bytes */
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@ -48,11 +49,13 @@ struct rcar_du_output_routing {
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* @features: device features (RCAR_DU_FEATURE_*)
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* @num_crtcs: total number of CRTCs
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* @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
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* @num_lvds: number of internal LVDS encoders
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*/
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struct rcar_du_device_info {
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unsigned int features;
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unsigned int num_crtcs;
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struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
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unsigned int num_lvds;
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};
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struct rcar_du_device {
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@ -70,6 +73,7 @@ struct rcar_du_device {
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struct rcar_du_group groups[2];
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unsigned int dpad0_source;
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struct rcar_du_lvdsenc *lvds[2];
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};
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static inline bool rcar_du_has(struct rcar_du_device *rcdu,
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@ -11,6 +11,8 @@
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* (at your option) any later version.
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*/
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#include <linux/export.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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@ -19,6 +21,7 @@
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#include "rcar_du_encoder.h"
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#include "rcar_du_kms.h"
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#include "rcar_du_lvdscon.h"
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#include "rcar_du_lvdsenc.h"
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#include "rcar_du_vgacon.h"
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/* -----------------------------------------------------------------------------
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@ -39,12 +42,17 @@ rcar_du_connector_best_encoder(struct drm_connector *connector)
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static void rcar_du_encoder_dpms(struct drm_encoder *encoder, int mode)
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{
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struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
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if (renc->lvds)
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rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc, mode);
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}
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static bool rcar_du_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
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const struct drm_display_mode *panel_mode;
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struct drm_device *dev = encoder->dev;
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struct drm_connector *connector;
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@ -82,15 +90,32 @@ static bool rcar_du_encoder_mode_fixup(struct drm_encoder *encoder,
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/* The flat panel mode is fixed, just copy it to the adjusted mode. */
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drm_mode_copy(adjusted_mode, panel_mode);
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/* The internal LVDS encoder has a clock frequency operating range of
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* 30MHz to 150MHz. Clamp the clock accordingly.
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*/
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if (renc->lvds)
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adjusted_mode->clock = clamp(adjusted_mode->clock,
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30000, 150000);
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return true;
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}
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static void rcar_du_encoder_mode_prepare(struct drm_encoder *encoder)
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{
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struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
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if (renc->lvds)
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rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc,
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DRM_MODE_DPMS_OFF);
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}
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static void rcar_du_encoder_mode_commit(struct drm_encoder *encoder)
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{
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struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
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if (renc->lvds)
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rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc,
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DRM_MODE_DPMS_ON);
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}
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static void rcar_du_encoder_mode_set(struct drm_encoder *encoder,
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@ -129,6 +154,19 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
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renc->output = output;
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switch (output) {
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case RCAR_DU_OUTPUT_LVDS0:
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renc->lvds = rcdu->lvds[0];
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break;
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case RCAR_DU_OUTPUT_LVDS1:
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renc->lvds = rcdu->lvds[1];
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break;
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default:
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break;
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}
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switch (type) {
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case RCAR_DU_ENCODER_VGA:
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encoder_type = DRM_MODE_ENCODER_DAC;
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@ -19,10 +19,12 @@
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#include <drm/drm_crtc.h>
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struct rcar_du_device;
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struct rcar_du_lvdsenc;
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struct rcar_du_encoder {
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struct drm_encoder encoder;
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enum rcar_du_output output;
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struct rcar_du_lvdsenc *lvds;
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};
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#define to_rcar_encoder(e) \
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@ -21,6 +21,7 @@
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#include "rcar_du_drv.h"
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#include "rcar_du_encoder.h"
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#include "rcar_du_kms.h"
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#include "rcar_du_lvdsenc.h"
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#include "rcar_du_regs.h"
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/* -----------------------------------------------------------------------------
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@ -217,6 +218,10 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
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}
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/* Initialize the encoders. */
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ret = rcar_du_lvdsenc_init(rcdu);
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if (ret < 0)
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return ret;
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for (i = 0; i < rcdu->pdata->num_encoders; ++i) {
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const struct rcar_du_encoder_data *pdata =
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&rcdu->pdata->encoders[i];
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196
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
Normal file
196
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
Normal file
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@ -0,0 +1,196 @@
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/*
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* rcar_du_lvdsenc.c -- R-Car Display Unit LVDS Encoder
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*
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* Copyright (C) 2013 Renesas Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "rcar_du_drv.h"
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#include "rcar_du_encoder.h"
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#include "rcar_du_lvdsenc.h"
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#include "rcar_lvds_regs.h"
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struct rcar_du_lvdsenc {
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struct rcar_du_device *dev;
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unsigned int index;
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void __iomem *mmio;
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struct clk *clock;
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int dpms;
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enum rcar_lvds_input input;
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};
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static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
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{
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iowrite32(data, lvds->mmio + reg);
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}
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static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.mode;
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unsigned int freq = mode->clock;
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u32 lvdcr0;
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u32 pllcr;
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int ret;
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if (lvds->dpms == DRM_MODE_DPMS_ON)
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return 0;
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ret = clk_prepare_enable(lvds->clock);
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if (ret < 0)
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return ret;
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/* PLL clock configuration */
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if (freq <= 38000)
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pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
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else if (freq <= 60000)
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pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
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else if (freq <= 121000)
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pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
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else
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pllcr = LVDPLLCR_PLLDLYCNT_150M;
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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/* Hardcode the channels and control signals routing for now.
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*
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* HSYNC -> CTRL0
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* VSYNC -> CTRL1
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* DISP -> CTRL2
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* 0 -> CTRL3
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*
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* Channels 1 and 3 are switched on ES1.
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*/
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rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
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LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
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LVDCTRCR_CTR0SEL_HSYNC);
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rcar_lvds_write(lvds, LVDCHCR,
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LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3) |
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LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1));
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/* Select the input, hardcode mode 0, enable LVDS operation and turn
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* bias circuitry on.
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*/
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lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN;
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if (rcrtc->index == 2)
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lvdcr0 |= LVDCR0_DUSEL;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1, LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
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LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
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/* Turn the PLL on, wait for the startup delay, and turn the output
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* on.
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*/
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lvdcr0 |= LVDCR0_PLLEN;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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usleep_range(100, 150);
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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lvds->dpms = DRM_MODE_DPMS_ON;
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return 0;
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}
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static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
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{
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if (lvds->dpms == DRM_MODE_DPMS_OFF)
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return;
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rcar_lvds_write(lvds, LVDCR0, 0);
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rcar_lvds_write(lvds, LVDCR1, 0);
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clk_disable_unprepare(lvds->clock);
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lvds->dpms = DRM_MODE_DPMS_OFF;
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}
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int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
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struct drm_crtc *crtc, int mode)
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{
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if (mode == DRM_MODE_DPMS_OFF) {
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rcar_du_lvdsenc_stop(lvds);
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return 0;
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} else if (crtc) {
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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return rcar_du_lvdsenc_start(lvds, rcrtc);
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} else
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return -EINVAL;
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}
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static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
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struct platform_device *pdev)
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{
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struct resource *mem;
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char name[7];
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sprintf(name, "lvds.%u", lvds->index);
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mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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if (mem == NULL) {
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dev_err(&pdev->dev, "failed to get memory resource for %s\n",
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name);
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return -EINVAL;
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}
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lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
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if (lvds->mmio == NULL) {
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dev_err(&pdev->dev, "failed to remap memory resource for %s\n",
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name);
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return -ENOMEM;
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}
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lvds->clock = devm_clk_get(&pdev->dev, name);
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if (IS_ERR(lvds->clock)) {
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dev_err(&pdev->dev, "failed to get clock for %s\n", name);
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return PTR_ERR(lvds->clock);
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}
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return 0;
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}
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int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
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{
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struct platform_device *pdev = to_platform_device(rcdu->dev);
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struct rcar_du_lvdsenc *lvds;
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unsigned int i;
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int ret;
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for (i = 0; i < rcdu->info->num_lvds; ++i) {
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lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
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if (lvds == NULL) {
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dev_err(&pdev->dev, "failed to allocate private data\n");
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return -ENOMEM;
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}
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lvds->dev = rcdu;
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lvds->index = i;
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lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
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lvds->dpms = DRM_MODE_DPMS_OFF;
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ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
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if (ret < 0)
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return ret;
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rcdu->lvds[i] = lvds;
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}
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return 0;
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}
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46
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
Normal file
46
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
Normal file
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/*
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* rcar_du_lvdsenc.h -- R-Car Display Unit LVDS Encoder
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*
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* Copyright (C) 2013 Renesas Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __RCAR_DU_LVDSENC_H__
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#define __RCAR_DU_LVDSENC_H__
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_data/rcar-du.h>
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struct rcar_drm_crtc;
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struct rcar_du_lvdsenc;
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enum rcar_lvds_input {
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RCAR_LVDS_INPUT_DU0,
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RCAR_LVDS_INPUT_DU1,
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RCAR_LVDS_INPUT_DU2,
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||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_DRM_RCAR_LVDS)
|
||||
int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu);
|
||||
int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
|
||||
struct drm_crtc *crtc, int mode);
|
||||
#else
|
||||
static inline int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
|
||||
struct drm_crtc *crtc, int mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __RCAR_DU_LVDSENC_H__ */
|
69
drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
Normal file
69
drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
Normal file
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* rcar_lvds_regs.h -- R-Car LVDS Interface Registers Definitions
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
*
|
||||
* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __RCAR_LVDS_REGS_H__
|
||||
#define __RCAR_LVDS_REGS_H__
|
||||
|
||||
#define LVDCR0 0x0000
|
||||
#define LVDCR0_DUSEL (1 << 15)
|
||||
#define LVDCR0_DMD (1 << 12)
|
||||
#define LVDCR0_LVMD_MASK (0xf << 8)
|
||||
#define LVDCR0_LVMD_SHIFT 8
|
||||
#define LVDCR0_PLLEN (1 << 4)
|
||||
#define LVDCR0_BEN (1 << 2)
|
||||
#define LVDCR0_LVEN (1 << 1)
|
||||
#define LVDCR0_LVRES (1 << 0)
|
||||
|
||||
#define LVDCR1 0x0004
|
||||
#define LVDCR1_CKSEL (1 << 15)
|
||||
#define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2))
|
||||
#define LVDCR1_CLKSTBY (3 << 0)
|
||||
|
||||
#define LVDPLLCR 0x0008
|
||||
#define LVDPLLCR_CEEN (1 << 14)
|
||||
#define LVDPLLCR_FBEN (1 << 13)
|
||||
#define LVDPLLCR_COSEL (1 << 12)
|
||||
#define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_MASK (0x7ff << 0)
|
||||
|
||||
#define LVDCTRCR 0x000c
|
||||
#define LVDCTRCR_CTR3SEL_ZERO (0 << 12)
|
||||
#define LVDCTRCR_CTR3SEL_ODD (1 << 12)
|
||||
#define LVDCTRCR_CTR3SEL_CDE (2 << 12)
|
||||
#define LVDCTRCR_CTR3SEL_MASK (7 << 12)
|
||||
#define LVDCTRCR_CTR2SEL_DISP (0 << 8)
|
||||
#define LVDCTRCR_CTR2SEL_ODD (1 << 8)
|
||||
#define LVDCTRCR_CTR2SEL_CDE (2 << 8)
|
||||
#define LVDCTRCR_CTR2SEL_HSYNC (3 << 8)
|
||||
#define LVDCTRCR_CTR2SEL_VSYNC (4 << 8)
|
||||
#define LVDCTRCR_CTR2SEL_MASK (7 << 8)
|
||||
#define LVDCTRCR_CTR1SEL_VSYNC (0 << 4)
|
||||
#define LVDCTRCR_CTR1SEL_DISP (1 << 4)
|
||||
#define LVDCTRCR_CTR1SEL_ODD (2 << 4)
|
||||
#define LVDCTRCR_CTR1SEL_CDE (3 << 4)
|
||||
#define LVDCTRCR_CTR1SEL_HSYNC (4 << 4)
|
||||
#define LVDCTRCR_CTR1SEL_MASK (7 << 4)
|
||||
#define LVDCTRCR_CTR0SEL_HSYNC (0 << 0)
|
||||
#define LVDCTRCR_CTR0SEL_VSYNC (1 << 0)
|
||||
#define LVDCTRCR_CTR0SEL_DISP (2 << 0)
|
||||
#define LVDCTRCR_CTR0SEL_ODD (3 << 0)
|
||||
#define LVDCTRCR_CTR0SEL_CDE (4 << 0)
|
||||
#define LVDCTRCR_CTR0SEL_MASK (7 << 0)
|
||||
|
||||
#define LVDCHCR 0x0010
|
||||
#define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) * 4))
|
||||
#define LVDCHCR_CHSEL_MASK(n) (3 << ((n) * 4))
|
||||
|
||||
#endif /* __RCAR_LVDS_REGS_H__ */
|
Loading…
Reference in a new issue