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thermal: exynos: Add thermal configuration data for exynos5440 TMU sensor
This patch adds configuration data for exynos5440 soc. Also register definations for the controller are added. Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Acked-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
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3 changed files with 82 additions and 0 deletions
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@ -456,6 +456,10 @@ static const struct of_device_id exynos_tmu_match[] = {
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.compatible = "samsung,exynos5250-tmu",
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.data = (void *)EXYNOS5250_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5440-tmu",
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.data = (void *)EXYNOS5440_TMU_DRV_DATA,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, exynos_tmu_match);
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@ -175,3 +175,74 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
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.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
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.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
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.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
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.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
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.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
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.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
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.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
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.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
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.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
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.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
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.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
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.inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
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.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
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.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
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.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
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.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.tmu_pmin = EXYNOS5440_TMU_PMIN,
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};
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#define EXYNOS5440_TMU_DATA \
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.trigger_levels[0] = 100, \
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.trigger_levels[4] = 105, \
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.trigger_enable[0] = 1, \
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.trigger_type[0] = SW_TRIP, \
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.trigger_type[4] = HW_TRIP, \
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.max_trigger_level = 5, \
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.gain = 5, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.cal_mode = 0, \
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.efuse_value = 0x5b2d, \
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.min_efuse_value = 16, \
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.max_efuse_value = 76, \
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.first_point_trim = 25, \
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.second_point_trim = 70, \
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.default_temp_offset = 25, \
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.type = SOC_ARCH_EXYNOS5440, \
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.registers = &exynos5440_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
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TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
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struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5440_TMU_DATA } ,
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{ EXYNOS5440_TMU_DATA } ,
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{ EXYNOS5440_TMU_DATA } ,
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},
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.tmu_count = 3,
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};
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#endif
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@ -143,4 +143,11 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
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#define EXYNOS5250_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
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#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
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#else
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#define EXYNOS5440_TMU_DRV_DATA (NULL)
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#endif
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#endif /*_EXYNOS_TMU_DATA_H*/
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