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PCI: designware: Make "num-lanes" an optional DT property
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used if we call dw_pcie_setup_rc() while bringing up the link. If the link has already been brought up by firmware, we need not call dw_pcie_setup_rc(), and "num-lanes" is unnecessary. Only complain about "num-lanes" if we actually need it and we didn't find a valid value. [bhelgaas: changelog] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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2 changed files with 8 additions and 5 deletions
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@ -14,7 +14,6 @@ Required properties:
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- num-lanes: number of lanes to use
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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@ -22,6 +21,8 @@ Required properties:
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- "pcie_bus"
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Optional properties:
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- num-lanes: number of lanes to use (this property should be specified unless
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the link is brought already up in BIOS)
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- reset-gpio: gpio pin number of power good signal
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
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specify this property, to keep backwards compatibility a range of 0x00-0xff
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@ -534,10 +534,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
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}
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}
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if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
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dev_err(pp->dev, "Failed to parse the number of lanes\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
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if (ret)
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pp->lanes = 0;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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if (!pp->ops->msi_host_init) {
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@ -814,6 +813,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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case 8:
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val |= PORT_LINK_MODE_8_LANES;
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break;
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default:
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dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
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return;
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}
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dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
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