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drm/i915: Handle async cancellation in sentinel assert

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With the watchdog cancelling requests asynchronously to preempt-to-busy we
need to relax one assert making it apply only to requests not in error.

v2:
 * Check against the correct request!

v3:
 * Simplify the check to avoid the question of when to sample the fence
   error vs sentinel bit.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20210324121335.2307063-5-tvrtko.ursulin@linux.intel.com
This commit is contained in:
Tvrtko Ursulin 2021-03-24 12:13:32 +00:00 committed by Daniel Vetter
parent 8f922e4227
commit 90a79a91dc
1 changed files with 8 additions and 4 deletions
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12
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
View file

@ -757,9 +757,8 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
{
struct intel_engine_cs *engine =
container_of(execlists, typeof(*engine), execlists);
struct i915_request * const *port, *rq;
struct i915_request * const *port, *rq, *prev = NULL;
struct intel_context *ce = NULL;
bool sentinel = false;
u32 ccid = -1;
trace_ports(execlists, msg, execlists->pending);
@ -809,15 +808,20 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
* Sentinels are supposed to be the last request so they flush
* the current execution off the HW. Check that they are the only
* request in the pending submission.
*
* NB: Due to the async nature of preempt-to-busy and request
* cancellation we need to handle the case where request
* becomes a sentinel in parallel to CSB processing.
*/
if (sentinel) {
if (prev && i915_request_has_sentinel(prev) &&
!READ_ONCE(prev->fence.error)) {
GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n",
engine->name,
ce->timeline->fence_context,
port - execlists->pending);
return false;
}
sentinel = i915_request_has_sentinel(rq);
prev = rq;
/*
* We want virtual requests to only be in the first slot so