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net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows not only setting up pri:tc mapping, but also configuring TX shapers on external port FIFOs. The K3 CPSW MQPRIO Qdisc offload is expected to work with VLAN/priority tagged packets. Non-tagged packets have to be mapped only to TC0. - TX traffic classes must be rated starting from TC that has highest priority and with no gaps - Traffic classes are used starting from 0, that has highest priority - min_rate defines Committed Information Rate (guaranteed) - max_rate defines Excess Information Rate (non guaranteed) and offloaded as (max_rate[i] - tcX_min_rate[i]) - VLAN/priority tagged packets mapped to TC0 will exit switch with VLAN tag priority 0 The configuration example: ethtool -L eth1 tx 5 ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \ map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \ queues 1@0 1@1 1@2 hw 1 mode channel \ shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \ map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1 ip link add link eth1 name eth1.100 type vlan id 100 ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7 In the above example two ports share the same TX CPPI queue 0 for low priority traffic. 3 traffic classes are defined for eth1 and mapped to: TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
569dce3f8e
commit
90bc21aaef
3 changed files with 311 additions and 1 deletions
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@ -633,6 +633,9 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
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/* restore vlan configurations */
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vlan_for_each(ndev, cpsw_restore_vlans, port);
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/* Initialize QoS */
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am65_cpsw_qos_mqprio_init(port);
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phylink_start(port->slave.phylink);
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return 0;
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@ -17,9 +17,12 @@
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#define AM65_CPSW_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_TX_PRI_MAP 0x018
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#define AM65_CPSW_PN_REG_RX_PRI_MAP 0x020
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#define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
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#define AM65_CPSW_PN_REG_EST_CTL 0x060
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#define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
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#define AM65_CPSW_PN_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
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/* AM65_CPSW_REG_CTL register fields */
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#define AM65_CPSW_CTL_EST_EN BIT(18)
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@ -56,6 +59,12 @@ enum timer_act {
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TACT_SKIP_PROG, /* just buffer can be updated */
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};
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/* number of traffic classes (FIFOs) per port */
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#define AM65_CPSW_PN_TC_NUM 8
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#define AM65_CPSW_PN_TX_PRI_MAP_DEFAULT 0x76543210
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static int am65_cpsw_setup_mqprio(struct net_device *ndev, void *type_data);
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static int am65_cpsw_port_est_enabled(struct am65_cpsw_port *port)
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{
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return port->qos.est_oper || port->qos.est_admin;
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@ -541,7 +550,6 @@ static void am65_cpsw_est_link_up(struct net_device *ndev, int link_speed)
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ktime_t cur_time;
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s64 delta;
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port->qos.link_speed = link_speed;
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if (!am65_cpsw_port_est_enabled(port))
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return;
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@ -795,6 +803,8 @@ int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
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return am65_cpsw_tc_query_caps(ndev, type_data);
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case TC_SETUP_QDISC_TAPRIO:
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return am65_cpsw_setup_taprio(ndev, type_data);
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case TC_SETUP_QDISC_MQPRIO:
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return am65_cpsw_setup_mqprio(ndev, type_data);
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case TC_SETUP_BLOCK:
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return am65_cpsw_qos_setup_tc_block(ndev, type_data);
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default:
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@ -802,10 +812,15 @@ int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
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}
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}
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static void am65_cpsw_tx_pn_shaper_link_up(struct am65_cpsw_port *port);
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void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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port->qos.link_speed = link_speed;
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am65_cpsw_tx_pn_shaper_link_up(port);
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if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))
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return;
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@ -937,3 +952,281 @@ void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common)
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host->port_base + AM65_CPSW_PN_REG_PRI_CIR(tx_ch));
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}
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}
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static void am65_cpsw_tx_pn_shaper_apply(struct am65_cpsw_port *port)
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{
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struct am65_cpsw_mqprio *p_mqprio = &port->qos.mqprio;
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struct am65_cpsw_common *common = port->common;
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struct tc_mqprio_qopt_offload *mqprio;
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bool shaper_en;
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u32 rate_mbps;
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int i;
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mqprio = &p_mqprio->mqprio_hw;
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shaper_en = p_mqprio->shaper_en && !p_mqprio->shaper_susp;
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for (i = 0; i < mqprio->qopt.num_tc; i++) {
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rate_mbps = 0;
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if (shaper_en) {
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rate_mbps = mqprio->min_rate[i] * 8 / 1000000;
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rate_mbps = am65_cpsw_qos_tx_rate_calc(rate_mbps,
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common->bus_freq);
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}
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writel(rate_mbps,
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port->port_base + AM65_CPSW_PN_REG_PRI_CIR(i));
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}
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for (i = 0; i < mqprio->qopt.num_tc; i++) {
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rate_mbps = 0;
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if (shaper_en && mqprio->max_rate[i]) {
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rate_mbps = mqprio->max_rate[i] - mqprio->min_rate[i];
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rate_mbps = rate_mbps * 8 / 1000000;
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rate_mbps = am65_cpsw_qos_tx_rate_calc(rate_mbps,
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common->bus_freq);
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}
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writel(rate_mbps,
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port->port_base + AM65_CPSW_PN_REG_PRI_EIR(i));
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}
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}
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static void am65_cpsw_tx_pn_shaper_link_up(struct am65_cpsw_port *port)
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{
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struct am65_cpsw_mqprio *p_mqprio = &port->qos.mqprio;
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struct am65_cpsw_common *common = port->common;
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bool shaper_susp = false;
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if (!p_mqprio->enable || !p_mqprio->shaper_en)
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return;
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if (p_mqprio->max_rate_total > port->qos.link_speed)
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shaper_susp = true;
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if (p_mqprio->shaper_susp == shaper_susp)
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return;
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if (shaper_susp)
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dev_info(common->dev,
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"Port%u: total shaper tx rate > link speed - suspend shaper\n",
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port->port_id);
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else
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dev_info(common->dev,
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"Port%u: link recover - resume shaper\n",
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port->port_id);
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p_mqprio->shaper_susp = shaper_susp;
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am65_cpsw_tx_pn_shaper_apply(port);
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}
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void am65_cpsw_qos_mqprio_init(struct am65_cpsw_port *port)
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{
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struct am65_cpsw_host *host = am65_common_get_host(port->common);
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struct am65_cpsw_mqprio *p_mqprio = &port->qos.mqprio;
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struct tc_mqprio_qopt_offload *mqprio;
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u32 tx_prio_map = 0, rx_prio_map;
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int i, fifo;
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mqprio = &p_mqprio->mqprio_hw;
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rx_prio_map = readl(host->port_base + AM65_CPSW_PN_REG_RX_PRI_MAP);
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if (p_mqprio->enable) {
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for (i = 0; i < AM65_CPSW_PN_TC_NUM; i++) {
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fifo = mqprio->qopt.prio_tc_map[i];
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tx_prio_map |= fifo << (4 * i);
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}
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netdev_set_num_tc(port->ndev, mqprio->qopt.num_tc);
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for (i = 0; i < mqprio->qopt.num_tc; i++) {
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netdev_set_tc_queue(port->ndev, i,
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mqprio->qopt.count[i],
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mqprio->qopt.offset[i]);
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if (!i) {
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p_mqprio->tc0_q = mqprio->qopt.offset[i];
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rx_prio_map &= ~(0x7 << (4 * p_mqprio->tc0_q));
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}
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}
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} else {
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/* restore default configuration */
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netdev_reset_tc(port->ndev);
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tx_prio_map = AM65_CPSW_PN_TX_PRI_MAP_DEFAULT;
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rx_prio_map |= p_mqprio->tc0_q << (4 * p_mqprio->tc0_q);
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p_mqprio->tc0_q = 0;
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}
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writel(tx_prio_map,
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port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
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writel(rx_prio_map,
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host->port_base + AM65_CPSW_PN_REG_RX_PRI_MAP);
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am65_cpsw_tx_pn_shaper_apply(port);
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}
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static int am65_cpsw_mqprio_verify(struct am65_cpsw_port *port,
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struct tc_mqprio_qopt_offload *mqprio)
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{
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int i;
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for (i = 0; i < mqprio->qopt.num_tc; i++) {
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unsigned int last = mqprio->qopt.offset[i] +
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mqprio->qopt.count[i];
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if (mqprio->qopt.offset[i] >= port->ndev->real_num_tx_queues ||
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!mqprio->qopt.count[i] ||
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last > port->ndev->real_num_tx_queues)
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return -EINVAL;
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}
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return 0;
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}
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static int am65_cpsw_mqprio_verify_shaper(struct am65_cpsw_port *port,
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struct tc_mqprio_qopt_offload *mqprio,
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u64 *max_rate)
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{
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struct am65_cpsw_common *common = port->common;
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u64 min_rate_total = 0, max_rate_total = 0;
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u32 min_rate_msk = 0, max_rate_msk = 0;
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bool has_min_rate, has_max_rate;
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int num_tc, i;
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has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE);
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has_max_rate = !!(mqprio->flags & TC_MQPRIO_F_MAX_RATE);
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if (!has_min_rate && has_max_rate)
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return -EOPNOTSUPP;
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if (!has_min_rate)
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return 0;
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num_tc = mqprio->qopt.num_tc;
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for (i = num_tc - 1; i >= 0; i--) {
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u32 ch_msk;
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if (mqprio->min_rate[i])
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min_rate_msk |= BIT(i);
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min_rate_total += mqprio->min_rate[i];
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if (has_max_rate) {
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if (mqprio->max_rate[i])
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max_rate_msk |= BIT(i);
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max_rate_total += mqprio->max_rate[i];
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if (!mqprio->min_rate[i] && mqprio->max_rate[i]) {
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dev_err(common->dev, "TX tc%d rate max>0 but min=0\n",
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i);
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return -EINVAL;
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}
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if (mqprio->max_rate[i] &&
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mqprio->max_rate[i] < mqprio->min_rate[i]) {
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dev_err(common->dev, "TX tc%d rate min(%llu)>max(%llu)\n",
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i, mqprio->min_rate[i],
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mqprio->max_rate[i]);
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return -EINVAL;
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}
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}
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ch_msk = GENMASK(num_tc - 1, i);
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if ((min_rate_msk & BIT(i)) && (min_rate_msk ^ ch_msk)) {
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dev_err(common->dev, "TX Min rate limiting has to be enabled sequentially hi->lo tx_rate_msk%x\n",
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min_rate_msk);
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return -EINVAL;
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}
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if ((max_rate_msk & BIT(i)) && (max_rate_msk ^ ch_msk)) {
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dev_err(common->dev, "TX max rate limiting has to be enabled sequentially hi->lo tx_rate_msk%x\n",
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max_rate_msk);
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return -EINVAL;
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}
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}
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min_rate_total *= 8;
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min_rate_total /= 1000 * 1000;
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max_rate_total *= 8;
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max_rate_total /= 1000 * 1000;
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if (port->qos.link_speed != SPEED_UNKNOWN) {
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if (min_rate_total > port->qos.link_speed) {
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dev_err(common->dev, "TX rate min exceed %llu link speed %d\n",
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min_rate_total, port->qos.link_speed);
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return -EINVAL;
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}
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if (max_rate_total > port->qos.link_speed) {
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dev_err(common->dev, "TX rate max exceed %llu link speed %d\n",
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max_rate_total, port->qos.link_speed);
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return -EINVAL;
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}
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}
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*max_rate = max_t(u64, min_rate_total, max_rate_total);
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return 0;
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}
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static int am65_cpsw_setup_mqprio(struct net_device *ndev, void *type_data)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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struct tc_mqprio_qopt_offload *mqprio = type_data;
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struct am65_cpsw_common *common = port->common;
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struct am65_cpsw_mqprio *p_mqprio;
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bool has_min_rate;
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int num_tc, ret;
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u64 max_rate;
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p_mqprio = &port->qos.mqprio;
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if (!mqprio->qopt.hw)
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goto skip_check;
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if (mqprio->mode != TC_MQPRIO_MODE_CHANNEL)
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return -EOPNOTSUPP;
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num_tc = mqprio->qopt.num_tc;
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if (num_tc > AM65_CPSW_PN_TC_NUM)
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return -ERANGE;
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if ((mqprio->flags & TC_MQPRIO_F_SHAPER) &&
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mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE)
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return -EOPNOTSUPP;
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ret = am65_cpsw_mqprio_verify(port, mqprio);
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if (ret)
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return ret;
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ret = am65_cpsw_mqprio_verify_shaper(port, mqprio, &max_rate);
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if (ret)
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return ret;
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skip_check:
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ret = pm_runtime_get_sync(common->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(common->dev);
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return ret;
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}
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if (mqprio->qopt.hw) {
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memcpy(&p_mqprio->mqprio_hw, mqprio, sizeof(*mqprio));
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has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE);
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p_mqprio->enable = 1;
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p_mqprio->shaper_en = has_min_rate;
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p_mqprio->shaper_susp = !has_min_rate;
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p_mqprio->max_rate_total = max_rate;
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} else {
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unsigned int tc0_q = p_mqprio->tc0_q;
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memset(p_mqprio, 0, sizeof(*p_mqprio));
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p_mqprio->mqprio_hw.qopt.num_tc = AM65_CPSW_PN_TC_NUM;
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p_mqprio->tc0_q = tc0_q;
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}
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if (!netif_running(ndev))
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goto exit_put;
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am65_cpsw_qos_mqprio_init(port);
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exit_put:
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pm_runtime_put(common->dev);
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return 0;
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}
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@ -7,8 +7,10 @@
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#include <linux/netdevice.h>
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#include <net/pkt_sched.h>
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#include <net/pkt_cls.h>
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struct am65_cpsw_common;
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struct am65_cpsw_port;
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struct am65_cpsw_est {
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int buf;
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@ -16,6 +18,16 @@ struct am65_cpsw_est {
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struct tc_taprio_qopt_offload taprio;
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};
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struct am65_cpsw_mqprio {
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struct tc_mqprio_qopt_offload mqprio_hw;
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u64 max_rate_total;
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unsigned enable:1;
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unsigned shaper_en:1;
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unsigned shaper_susp:1;
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unsigned tc0_q:3;
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};
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struct am65_cpsw_ale_ratelimit {
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unsigned long cookie;
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u64 rate_packet_ps;
|
||||
|
@ -26,6 +38,7 @@ struct am65_cpsw_qos {
|
|||
struct am65_cpsw_est *est_oper;
|
||||
ktime_t link_down_time;
|
||||
int link_speed;
|
||||
struct am65_cpsw_mqprio mqprio;
|
||||
|
||||
struct am65_cpsw_ale_ratelimit ale_bc_ratelimit;
|
||||
struct am65_cpsw_ale_ratelimit ale_mc_ratelimit;
|
||||
|
@ -35,6 +48,7 @@ int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
|||
void *type_data);
|
||||
void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed);
|
||||
void am65_cpsw_qos_link_down(struct net_device *ndev);
|
||||
void am65_cpsw_qos_mqprio_init(struct am65_cpsw_port *port);
|
||||
int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev, int queue, u32 rate_mbps);
|
||||
void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common);
|
||||
|
||||
|
|
Loading…
Reference in a new issue