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tile PCI RC: support more MSI-X interrupt vectors
To support PCIe devices with higher number of MSI-X interrupt vectors, e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more vectors in addition to ~10 from the Map Mem regions. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
parent
803c874abe
commit
90d9dd6695
4 changed files with 106 additions and 20 deletions
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@ -61,6 +61,29 @@ int gxio_trio_alloc_memory_maps(gxio_trio_context_t * context,
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EXPORT_SYMBOL(gxio_trio_alloc_memory_maps);
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struct alloc_scatter_queues_param {
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unsigned int count;
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unsigned int first;
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unsigned int flags;
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};
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int gxio_trio_alloc_scatter_queues(gxio_trio_context_t * context,
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unsigned int count, unsigned int first,
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unsigned int flags)
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{
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struct alloc_scatter_queues_param temp;
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struct alloc_scatter_queues_param *params = &temp;
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params->count = count;
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params->first = first;
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params->flags = flags;
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return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
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sizeof(*params),
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GXIO_TRIO_OP_ALLOC_SCATTER_QUEUES);
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}
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EXPORT_SYMBOL(gxio_trio_alloc_scatter_queues);
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struct alloc_pio_regions_param {
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unsigned int count;
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@ -22,6 +22,45 @@
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#ifndef __ASSEMBLER__
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/*
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* Map SQ Doorbell Format.
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* This describes the format of the write-only doorbell register that exists
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* in the last 8-bytes of the MAP_SQ_BASE/LIM range. This register is only
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* writable from PCIe space. Writes to this register will not be written to
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* Tile memory space and thus no IO VA translation is required if the last
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* page of the BASE/LIM range is not otherwise written.
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*/
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/*
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* When written with a 1, the associated MAP_SQ region's doorbell
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* interrupt will be triggered once all previous writes are visible to
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* Tile software.
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*/
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uint_reg_t doorbell : 1;
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/*
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* When written with a 1, the descriptor at the head of the associated
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* MAP_SQ's FIFO will be dequeued.
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*/
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uint_reg_t pop : 1;
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/* Reserved. */
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uint_reg_t __reserved : 62;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved : 62;
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uint_reg_t pop : 1;
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uint_reg_t doorbell : 1;
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#endif
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};
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uint_reg_t word;
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} TRIO_MAP_SQ_DOORBELL_FMT_t;
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/*
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* Tile PIO Region Configuration - CFG Address Format.
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* This register describes the address format for PIO accesses when the
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@ -30,6 +30,7 @@
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#define GXIO_TRIO_OP_ALLOC_MEMORY_MAPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1404)
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#define GXIO_TRIO_OP_ALLOC_SCATTER_QUEUES IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140e)
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#define GXIO_TRIO_OP_ALLOC_PIO_REGIONS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1412)
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#define GXIO_TRIO_OP_INIT_PIO_REGION_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1414)
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@ -54,6 +55,10 @@ int gxio_trio_alloc_memory_maps(gxio_trio_context_t * context,
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unsigned int flags);
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int gxio_trio_alloc_scatter_queues(gxio_trio_context_t * context,
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unsigned int count, unsigned int first,
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unsigned int flags);
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int gxio_trio_alloc_pio_regions(gxio_trio_context_t * context,
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unsigned int count, unsigned int first,
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unsigned int flags);
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@ -1474,32 +1474,55 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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trio_context = controller->trio;
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/*
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* Allocate the Mem-Map that will accept the MSI write and
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* trigger the TILE-side interrupts.
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* Allocate a scatter-queue that will accept the MSI write and
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* trigger the TILE-side interrupts. We use the scatter-queue regions
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* before the mem map regions, because the latter are needed by more
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* applications.
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*/
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mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
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if (mem_map < 0) {
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dev_printk(KERN_INFO, &pdev->dev,
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"%s Mem-Map alloc failure. "
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"Failed to initialize MSI interrupts. "
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"Falling back to legacy interrupts.\n",
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desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
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mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
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if (mem_map >= 0) {
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TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
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.pop = 0,
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.doorbell = 1,
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}};
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ret = -ENOMEM;
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goto msi_mem_map_alloc_failure;
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mem_map += TRIO_NUM_MAP_MEM_REGIONS;
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mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
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mem_map * MEM_MAP_INTR_REGION_SIZE;
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mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
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msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
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msg.data = (unsigned int)doorbell_template.word;
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} else {
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/* SQ regions are out, allocate from map mem regions. */
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mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
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if (mem_map < 0) {
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dev_printk(KERN_INFO, &pdev->dev,
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"%s Mem-Map alloc failure. "
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"Failed to initialize MSI interrupts. "
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"Falling back to legacy interrupts.\n",
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desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
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ret = -ENOMEM;
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goto msi_mem_map_alloc_failure;
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}
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mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
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mem_map * MEM_MAP_INTR_REGION_SIZE;
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mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
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msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
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TRIO_MAP_MEM_REG_INT0;
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msg.data = mem_map;
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}
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/* We try to distribute different IRQs to different tiles. */
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cpu = tile_irq_cpu(irq);
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/*
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* Now call up to the HV to configure the Mem-Map interrupt and
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* Now call up to the HV to configure the MSI interrupt and
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* set up the IPI binding.
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*/
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mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
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mem_map * MEM_MAP_INTR_REGION_SIZE;
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mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
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ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
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KERNEL_PL, irq, controller->mac,
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mem_map, mem_map_base, mem_map_limit,
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@ -1512,13 +1535,9 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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irq_set_msi_desc(irq, desc);
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msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 - TRIO_MAP_MEM_REG_INT0;
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msg.address_hi = msi_addr >> 32;
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msg.address_lo = msi_addr & 0xffffffff;
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msg.data = mem_map;
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write_msi_msg(irq, &msg);
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irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
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irq_set_handler_data(irq, controller);
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