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gpio: tqmx86: fix broken IRQ_TYPE_EDGE_BOTH interrupt type
The TQMx86 GPIO controller only supports falling and rising edge
triggers, but not both. Fix this by implementing a software both-edge
mode that toggles the edge type after every interrupt.
Fixes: b868db94a6
("gpio: tqmx86: Add GPIO from for this IO controller")
Co-developed-by: Gregor Herburger <gregor.herburger@tq-group.com>
Signed-off-by: Gregor Herburger <gregor.herburger@tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/515324f0491c4d44f4ef49f170354aca002d81ef.1717063994.git.matthias.schiffer@ew.tq-group.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
parent
08af509efd
commit
90dd7de4ef
1 changed files with 42 additions and 4 deletions
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@ -32,6 +32,10 @@
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#define TQMX86_GPII_NONE 0
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#define TQMX86_GPII_FALLING BIT(0)
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#define TQMX86_GPII_RISING BIT(1)
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/* Stored in irq_type as a trigger type, but not actually valid as a register
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* value, so the name doesn't use "GPII"
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*/
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#define TQMX86_INT_BOTH (BIT(0) | BIT(1))
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#define TQMX86_GPII_MASK (BIT(0) | BIT(1))
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#define TQMX86_GPII_BITS 2
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/* Stored in irq_type with GPII bits */
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@ -113,9 +117,15 @@ static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset)
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{
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u8 type = TQMX86_GPII_NONE, gpiic;
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if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED)
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if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED) {
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type = gpio->irq_type[offset] & TQMX86_GPII_MASK;
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if (type == TQMX86_INT_BOTH)
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type = tqmx86_gpio_get(&gpio->chip, offset + TQMX86_NGPO)
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? TQMX86_GPII_FALLING
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: TQMX86_GPII_RISING;
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}
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gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
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gpiic &= ~(TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS));
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gpiic |= type << (offset * TQMX86_GPII_BITS);
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@ -169,7 +179,7 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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new_type = TQMX86_GPII_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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new_type = TQMX86_GPII_FALLING | TQMX86_GPII_RISING;
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new_type = TQMX86_INT_BOTH;
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break;
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default:
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return -EINVAL; /* not supported */
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@ -189,8 +199,8 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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unsigned long irq_bits;
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int i = 0;
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unsigned long irq_bits, flags;
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int i;
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u8 irq_status;
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chained_irq_enter(irq_chip, desc);
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@ -199,6 +209,34 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
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tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
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irq_bits = irq_status;
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raw_spin_lock_irqsave(&gpio->spinlock, flags);
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for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
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/*
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* Edge-both triggers are implemented by flipping the edge
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* trigger after each interrupt, as the controller only supports
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* either rising or falling edge triggers, but not both.
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*
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* Internally, the TQMx86 GPIO controller has separate status
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* registers for rising and falling edge interrupts. GPIIC
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* configures which bits from which register are visible in the
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* interrupt status register GPIIS and defines what triggers the
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* parent IRQ line. Writing to GPIIS always clears both rising
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* and falling interrupt flags internally, regardless of the
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* currently configured trigger.
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*
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* In consequence, we can cleanly implement the edge-both
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* trigger in software by first clearing the interrupt and then
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* setting the new trigger based on the current GPIO input in
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* tqmx86_gpio_irq_config() - even if an edge arrives between
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* reading the input and setting the trigger, we will have a new
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* interrupt pending.
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*/
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if ((gpio->irq_type[i] & TQMX86_GPII_MASK) == TQMX86_INT_BOTH)
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tqmx86_gpio_irq_config(gpio, i);
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}
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raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
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for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
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generic_handle_domain_irq(gpio->chip.irq.domain,
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i + TQMX86_NGPO);
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