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[PATCH] ppc32: Add Yucca (440SPe eval board) platform
Add support for AMCC PowerPC 440SPe "Yucca" eval board platform. Signed-off-by: Roland Dreier <rolandd@cisco.com> Cc: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
parent
b0f7b8bc57
commit
90eb266584
7 changed files with 527 additions and 2 deletions
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@ -79,6 +79,12 @@ zimageinitrd-$(CONFIG_LUAN) := zImage.initrd-TREE
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entrypoint-$(CONFIG_LUAN) := 0x01000000
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extra.o-$(CONFIG_LUAN) := pibs.o
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zimage-$(CONFIG_YUCCA) := zImage-TREE
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zimageinitrd-$(CONFIG_YUCCA) := zImage.initrd-TREE
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end-$(CONFIG_YUCCA) := yucca
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entrypoint-$(CONFIG_YUCCA) := 0x01000000
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extra.o-$(CONFIG_YUCCA) := pibs.o
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zimage-$(CONFIG_OCOTEA) := zImage-TREE
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zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE
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end-$(CONFIG_OCOTEA) := ocotea
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@ -82,6 +82,12 @@ config LUAN
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help
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This option enables support for the IBM PPC440SP evaluation board.
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config YUCCA
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bool "Yucca"
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select WANT_EARLY_SERIAL
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help
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This option enables support for the AMCC PPC440SPe evaluation board.
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config OCOTEA
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bool "Ocotea"
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select WANT_EARLY_SERIAL
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@ -126,7 +132,8 @@ config 440SP
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config 440SPE
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bool
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default n
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depends on YUCCA
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default y
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config 440
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bool
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@ -162,7 +169,7 @@ config BOOKE
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config IBM_OCP
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bool
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depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
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depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
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default y
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config XILINX_OCP
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@ -7,6 +7,7 @@ obj-$(CONFIG_EBONY) += ebony.o
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obj-$(CONFIG_EP405) += ep405.o
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obj-$(CONFIG_BUBINGA) += bubinga.o
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obj-$(CONFIG_LUAN) += luan.o
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obj-$(CONFIG_YUCCA) += yucca.o
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obj-$(CONFIG_OCOTEA) += ocotea.o
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obj-$(CONFIG_REDWOOD_5) += redwood5.o
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obj-$(CONFIG_REDWOOD_6) += redwood6.o
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395
arch/ppc/platforms/4xx/yucca.c
Normal file
395
arch/ppc/platforms/4xx/yucca.c
Normal file
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@ -0,0 +1,395 @@
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/*
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* arch/ppc/platforms/4xx/yucca.c
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*
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* Yucca board specific routines
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*
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* Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
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*
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* Copyright 2004-2005 MontaVista Software Inc.
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/blkdev.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ocp.h>
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#include <asm/pci-bridge.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/ppcboot.h>
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#include <syslib/ibm44x_common.h>
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#include <syslib/ibm440gx_common.h>
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#include <syslib/ibm440sp_common.h>
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#include <syslib/ppc440spe_pcie.h>
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extern bd_t __res;
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static struct ibm44x_clocks clocks __initdata;
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static void __init
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yucca_calibrate_decr(void)
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{
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unsigned int freq;
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if (mfspr(SPRN_CCR1) & CCR1_TCS)
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freq = YUCCA_TMR_CLK;
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else
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freq = clocks.cpu;
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ibm44x_calibrate_decr(freq);
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}
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static int
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yucca_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: AMCC\n");
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seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
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return 0;
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}
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static enum {
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HOSE_UNKNOWN,
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HOSE_PCIX,
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HOSE_PCIE0,
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HOSE_PCIE1,
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HOSE_PCIE2
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} hose_type[4];
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static inline int
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yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
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if (hose_type[hose->index] == HOSE_PCIX) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
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};
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const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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} else if (hose_type[hose->index] == HOSE_PCIE0) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 96, 97, 98, 99 },
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};
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const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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} else if (hose_type[hose->index] == HOSE_PCIE1) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 100, 101, 102, 103 },
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};
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const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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} else if (hose_type[hose->index] == HOSE_PCIE2) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 104, 105, 106, 107 },
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};
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const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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return -1;
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}
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static void __init yucca_set_emacdata(void)
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{
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struct ocp_def *def;
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struct ocp_func_emac_data *emacdata;
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/* Set phy_map, phy_mode, and mac_addr for the EMAC */
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
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emacdata = def->additions;
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emacdata->phy_map = 0x00000001; /* Skip 0x00 */
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emacdata->phy_mode = PHY_MODE_GMII;
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memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
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}
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static int __init yucca_pcie_card_present(int port)
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{
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void __iomem *pcie_fpga_base;
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u16 reg;
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pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
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reg = in_be16(pcie_fpga_base + FPGA_REG1C);
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iounmap(pcie_fpga_base);
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switch(port) {
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case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
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case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
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case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
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default: return 0;
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}
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}
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/*
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* For the given slot, set rootpoint mode, send power to the slot,
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* turn on the green LED and turn off the yellow LED, enable the clock
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* and turn off reset.
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*/
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static void __init yucca_setup_pcie_fpga_rootpoint(int port)
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{
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void __iomem *pcie_reg_fpga_base;
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u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
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pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
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switch(port) {
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case 0:
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rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
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endpoint = 0;
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power = FPGA_REG1A_PE0_PWRON;
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green_led = FPGA_REG1A_PE0_GLED;
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clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
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yellow_led = FPGA_REG1A_PE0_YLED;
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reset_off = FPGA_REG1C_PE0_PERST;
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break;
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case 1:
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rootpoint = 0;
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endpoint = FPGA_REG1C_PE1_ENDPOINT;
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power = FPGA_REG1A_PE1_PWRON;
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green_led = FPGA_REG1A_PE1_GLED;
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clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
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yellow_led = FPGA_REG1A_PE1_YLED;
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reset_off = FPGA_REG1C_PE1_PERST;
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break;
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case 2:
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rootpoint = 0;
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endpoint = FPGA_REG1C_PE2_ENDPOINT;
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power = FPGA_REG1A_PE2_PWRON;
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green_led = FPGA_REG1A_PE2_GLED;
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clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
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yellow_led = FPGA_REG1A_PE2_YLED;
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reset_off = FPGA_REG1C_PE2_PERST;
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break;
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default:
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return;
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}
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out_be16(pcie_reg_fpga_base + FPGA_REG1A,
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~(power | clock | green_led) &
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(yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
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out_be16(pcie_reg_fpga_base + FPGA_REG1C,
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~(endpoint | reset_off) &
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(rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
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/*
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* Leave device in reset for a while after powering on the
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* slot to give it a chance to initialize.
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*/
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mdelay(250);
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out_be16(pcie_reg_fpga_base + FPGA_REG1C,
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reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
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iounmap(pcie_reg_fpga_base);
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}
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static void __init
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yucca_setup_hoses(void)
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{
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struct pci_controller *hose;
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char name[20];
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int i;
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if (0 && ppc440spe_init_pcie()) {
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printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
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return;
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}
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for (i = 0; i <= 2; ++i) {
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if (!yucca_pcie_card_present(i))
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continue;
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printk(KERN_INFO "PCIE%d: card present\n", i);
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yucca_setup_pcie_fpga_rootpoint(i);
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if (ppc440spe_init_pcie_rootport(i)) {
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printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
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continue;
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}
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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sprintf(name, "PCIE%d host bridge", i);
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pci_init_resource(&hose->io_resource,
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YUCCA_PCIX_LOWER_IO,
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YUCCA_PCIX_UPPER_IO,
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IORESOURCE_IO,
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name);
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hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
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i * YUCCA_PCIE_MEM_SIZE;
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hose->mem_space.end = hose->mem_space.start +
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YUCCA_PCIE_MEM_SIZE - 1;
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pci_init_resource(&hose->mem_resources[0],
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hose->mem_space.start,
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hose->mem_space.end,
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IORESOURCE_MEM,
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name);
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hose->first_busno = 0;
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hose->last_busno = 15;
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hose_type[hose->index] = HOSE_PCIE0 + i;
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ppc440spe_setup_pcie(hose, i);
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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}
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = yucca_map_irq;
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}
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TODC_ALLOC();
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static void __init
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yucca_early_serial_map(void)
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{
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struct uart_port port;
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/* Setup ioremapped serial port access */
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memset(&port, 0, sizeof(port));
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port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
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port.irq = UART0_INT;
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port.uartclk = clocks.uart0;
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port.regshift = 0;
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port.iotype = SERIAL_IO_MEM;
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port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
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port.line = 0;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 0 failed\n");
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}
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port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
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port.irq = UART1_INT;
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port.uartclk = clocks.uart1;
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port.line = 1;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 1 failed\n");
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}
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port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
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port.irq = UART2_INT;
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port.uartclk = BASE_BAUD;
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port.line = 2;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 2 failed\n");
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}
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}
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static void __init
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yucca_setup_arch(void)
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{
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yucca_set_emacdata();
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#if !defined(CONFIG_BDI_SWITCH)
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/*
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* The Abatron BDI JTAG debugger does not tolerate others
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* mucking with the debug registers.
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*/
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mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
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#endif
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/*
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* Determine various clocks.
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* To be completely correct we should get SysClk
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* from FPGA, because it can be changed by on-board switches
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* --ebs
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*/
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/* 440GX and 440SPe clocking is the same - rd */
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ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
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ocp_sys_info.opb_bus_freq = clocks.opb;
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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/* Setup PCIXn host bridges */
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yucca_setup_hoses();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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yucca_early_serial_map();
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/* Identify the system */
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printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
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}
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void __init platform_init(unsigned long r3, unsigned long r4,
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unsigned long r5, unsigned long r6, unsigned long r7)
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{
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ibm44x_platform_init(r3, r4, r5, r6, r7);
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ppc_md.setup_arch = yucca_setup_arch;
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ppc_md.show_cpuinfo = yucca_show_cpuinfo;
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ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
|
||||
ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
|
||||
|
||||
ppc_md.calibrate_decr = yucca_calibrate_decr;
|
||||
#ifdef CONFIG_KGDB
|
||||
ppc_md.early_serial_map = yucca_early_serial_map;
|
||||
#endif
|
||||
}
|
111
arch/ppc/platforms/4xx/yucca.h
Normal file
111
arch/ppc/platforms/4xx/yucca.h
Normal file
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* arch/ppc/platforms/4xx/yucca.h
|
||||
*
|
||||
* Yucca board definitions
|
||||
*
|
||||
* Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
|
||||
*
|
||||
* Copyright 2004-2005 MontaVista Software Inc.
|
||||
* Copyright (c) 2005 Cisco Systems. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_YUCCA_H__
|
||||
#define __ASM_YUCCA_H__
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <platforms/4xx/ppc440spe.h>
|
||||
|
||||
/* F/W TLB mapping used in bootloader glue to reset EMAC */
|
||||
#define PPC44x_EMAC0_MR0 0xa0000800
|
||||
|
||||
/* Location of MAC addresses in PIBS image */
|
||||
#define PIBS_FLASH_BASE 0xffe00000
|
||||
#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
|
||||
|
||||
/* External timer clock frequency */
|
||||
#define YUCCA_TMR_CLK 25000000
|
||||
|
||||
/*
|
||||
* FPGA registers
|
||||
*/
|
||||
#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL
|
||||
#define YUCCA_FPGA_REG_SIZE 0x24
|
||||
|
||||
#define FPGA_REG1A 0x1a
|
||||
|
||||
#define FPGA_REG1A_PE0_GLED 0x8000
|
||||
#define FPGA_REG1A_PE1_GLED 0x4000
|
||||
#define FPGA_REG1A_PE2_GLED 0x2000
|
||||
#define FPGA_REG1A_PE0_YLED 0x1000
|
||||
#define FPGA_REG1A_PE1_YLED 0x0800
|
||||
#define FPGA_REG1A_PE2_YLED 0x0400
|
||||
#define FPGA_REG1A_PE0_PWRON 0x0200
|
||||
#define FPGA_REG1A_PE1_PWRON 0x0100
|
||||
#define FPGA_REG1A_PE2_PWRON 0x0080
|
||||
#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
|
||||
#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
|
||||
#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
|
||||
#define FPGA_REG1A_PE_SPREAD0 0x0008
|
||||
#define FPGA_REG1A_PE_SPREAD1 0x0004
|
||||
#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
|
||||
#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
|
||||
|
||||
#define FPGA_REG1C 0x1c
|
||||
|
||||
#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
|
||||
#define FPGA_REG1C_PE1_ENDPOINT 0x4000
|
||||
#define FPGA_REG1C_PE2_ENDPOINT 0x2000
|
||||
#define FPGA_REG1C_PE0_PRSNT 0x1000
|
||||
#define FPGA_REG1C_PE1_PRSNT 0x0800
|
||||
#define FPGA_REG1C_PE2_PRSNT 0x0400
|
||||
#define FPGA_REG1C_PE0_WAKE 0x0080
|
||||
#define FPGA_REG1C_PE1_WAKE 0x0040
|
||||
#define FPGA_REG1C_PE2_WAKE 0x0020
|
||||
#define FPGA_REG1C_PE0_PERST 0x0010
|
||||
#define FPGA_REG1C_PE1_PERST 0x0008
|
||||
#define FPGA_REG1C_PE2_PERST 0x0004
|
||||
|
||||
/*
|
||||
* Serial port defines
|
||||
*/
|
||||
#define RS_TABLE_SIZE 3
|
||||
|
||||
/* PIBS defined UART mappings, used before early_serial_setup */
|
||||
#define UART0_IO_BASE 0xa0000200
|
||||
#define UART1_IO_BASE 0xa0000300
|
||||
#define UART2_IO_BASE 0xa0000600
|
||||
|
||||
#define BASE_BAUD 11059200
|
||||
#define STD_UART_OP(num) \
|
||||
{ 0, BASE_BAUD, 0, UART##num##_INT, \
|
||||
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
|
||||
iomem_base: (void*)UART##num##_IO_BASE, \
|
||||
io_type: SERIAL_IO_MEM},
|
||||
|
||||
#define SERIAL_PORT_DFNS \
|
||||
STD_UART_OP(0) \
|
||||
STD_UART_OP(1) \
|
||||
STD_UART_OP(2)
|
||||
|
||||
/* PCI support */
|
||||
#define YUCCA_PCIX_LOWER_IO 0x00000000
|
||||
#define YUCCA_PCIX_UPPER_IO 0x0000ffff
|
||||
#define YUCCA_PCIX_LOWER_MEM 0x80000000
|
||||
#define YUCCA_PCIX_UPPER_MEM 0x8fffffff
|
||||
#define YUCCA_PCIE_LOWER_MEM 0x90000000
|
||||
#define YUCCA_PCIE_MEM_SIZE 0x10000000
|
||||
|
||||
#define YUCCA_PCIX_MEM_SIZE 0x10000000
|
||||
#define YUCCA_PCIX_MEM_OFFSET 0x00000000
|
||||
#define YUCCA_PCIE_MEM_SIZE 0x10000000
|
||||
#define YUCCA_PCIE_MEM_OFFSET 0x00000000
|
||||
|
||||
#endif /* __ASM_YUCCA_H__ */
|
||||
#endif /* __KERNEL__ */
|
|
@ -54,6 +54,7 @@ obj-$(CONFIG_GT64260) += gt64260_pic.o
|
|||
obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o
|
||||
obj-$(CONFIG_HDPU) += pci_auto.o
|
||||
obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o
|
||||
obj-$(CONFIG_YUCCA) += pci_auto.o todc_time.o
|
||||
obj-$(CONFIG_KATANA) += pci_auto.o
|
||||
obj-$(CONFIG_MV64360) += mv64360_pic.o
|
||||
obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o
|
||||
|
|
|
@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
#include <platforms/4xx/luan.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_YUCCA)
|
||||
#include <platforms/4xx/yucca.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OCOTEA)
|
||||
#include <platforms/4xx/ocotea.h>
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue