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ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2 changed files with 6 additions and 1 deletions
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@ -4,7 +4,7 @@
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#ifndef __ASMARM_CACHE_H
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#ifndef __ASMARM_CACHE_H
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#define __ASMARM_CACHE_H
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#define __ASMARM_CACHE_H
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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/*
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@ -771,3 +771,8 @@ config CACHE_XSC3L2
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select OUTER_CACHE
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select OUTER_CACHE
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help
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help
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This option enables the L2 cache on XScale3.
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This option enables the L2 cache on XScale3.
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config ARM_L1_CACHE_SHIFT
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int
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default 6 if ARCH_OMAP3
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default 5
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