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drm/amd/pm: add Raven2 watermark WmType setting

Browse source 
Which tells it's a normal pstate change or memory retraining.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-09-03 15:42:59 +08:00 committed by Alex Deucher
parent ce2c00061b
commit 911779e3fc
2 changed files with 13 additions and 1 deletions
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3
drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h
View file

@ -54,7 +54,8 @@ typedef struct {
uint16_t MaxMclk;
uint8_t WmSetting;
uint8_t Padding[3];
uint8_t WmType;
uint8_t Padding[2];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4

11
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
View file

@ -1181,8 +1181,19 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct smu10_hwmgr *data = hwmgr->backend;
struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
Watermarks_t *table = &(data->water_marks_table);
struct amdgpu_device *adev = hwmgr->adev;
int i;
smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
for (i = 0; i < NUM_WM_RANGES; i++)
table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
for (i = 0; i < NUM_WM_RANGES; i++)
table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
}
smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
data->water_marks_exist = true;
return 0;