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drm/i915: disable wc gtt pte mappings on gen2
It doesn't work since the gtt pte range sits in the middle of the mmio
bar. We didn't notice that since both my and Chris' gen2 machines
don't support PAT and hence all wc io mapping request will
automatically be demoted to uc.
This regression has been introduce in
commit edef7e685d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Sep 14 11:57:47 2012 +0100
agp/intel: Use a write-combining map for updating PTEs
Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
1cf8378906
commit
9169d3a880
1 changed files with 1 additions and 1 deletions
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@ -667,7 +667,7 @@ static int intel_gtt_init(void)
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gtt_map_size = intel_private.base.gtt_total_entries * 4;
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gtt_map_size = intel_private.base.gtt_total_entries * 4;
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intel_private.gtt = NULL;
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intel_private.gtt = NULL;
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if (INTEL_GTT_GEN < 6)
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if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
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intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
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intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
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gtt_map_size);
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gtt_map_size);
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if (intel_private.gtt == NULL)
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if (intel_private.gtt == NULL)
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