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media: staging: tegra-vde: Replace debug messages with trace points
Trace points are much more efficient than debug messages for intensive tracing and could be conveniently enabled / disabled dynamically, hence let's replace debug messages with the trace points. This also makes code a bit cleaner. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Dmitry Osipenko
Mauro Carvalho Chehab
parent
c35f0b1653
commit
91dc5e91ed
2 changed files with 220 additions and 95 deletions
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@ -35,14 +35,6 @@
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#define BSE_ICMDQUE_EMPTY BIT(3)
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#define BSE_DMA_BUSY BIT(23)
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#define VDE_WR(__data, __addr) \
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do { \
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dev_dbg(vde->miscdev.parent, \
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"%s: %d: 0x%08X => " #__addr ")\n", \
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__func__, __LINE__, (u32)(__data)); \
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writel_relaxed(__data, __addr); \
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} while (0)
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struct video_frame {
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struct dma_buf_attachment *y_dmabuf_attachment;
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struct dma_buf_attachment *cb_dmabuf_attachment;
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@ -81,12 +73,66 @@ struct tegra_vde {
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u32 *iram;
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};
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static void tegra_vde_set_bits(struct tegra_vde *vde,
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u32 mask, void __iomem *regs)
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static __maybe_unused char const *
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tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base)
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{
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u32 value = readl_relaxed(regs);
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if (vde->sxe == base)
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return "SXE";
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VDE_WR(value | mask, regs);
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if (vde->bsev == base)
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return "BSEV";
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if (vde->mbe == base)
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return "MBE";
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if (vde->ppe == base)
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return "PPE";
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if (vde->mce == base)
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return "MCE";
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if (vde->tfe == base)
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return "TFE";
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if (vde->ppb == base)
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return "PPB";
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if (vde->vdma == base)
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return "VDMA";
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if (vde->frameid == base)
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return "FRAMEID";
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return "???";
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}
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#define CREATE_TRACE_POINTS
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#include "trace.h"
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static void tegra_vde_writel(struct tegra_vde *vde,
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u32 value, void __iomem *base, u32 offset)
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{
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trace_vde_writel(vde, base, offset, value);
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writel_relaxed(value, base + offset);
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}
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static u32 tegra_vde_readl(struct tegra_vde *vde,
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void __iomem *base, u32 offset)
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{
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u32 value = readl_relaxed(base + offset);
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trace_vde_readl(vde, base, offset, value);
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return value;
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}
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static void tegra_vde_set_bits(struct tegra_vde *vde,
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u32 mask, void __iomem *base, u32 offset)
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{
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u32 value = tegra_vde_readl(vde, base, offset);
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tegra_vde_writel(vde, value | mask, base, offset);
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}
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static int tegra_vde_wait_mbe(struct tegra_vde *vde)
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@ -107,8 +153,8 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
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unsigned int idx;
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int err;
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VDE_WR(0xD0000000 | (0 << 23), vde->mbe + 0x80);
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VDE_WR(0xD0200000 | (0 << 23), vde->mbe + 0x80);
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tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);
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tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);
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err = tegra_vde_wait_mbe(vde);
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if (err)
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@ -118,8 +164,10 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
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return 0;
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for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) {
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VDE_WR(0xD0000000 | (frame_idx << 23), vde->mbe + 0x80);
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VDE_WR(0xD0200000 | (frame_idx << 23), vde->mbe + 0x80);
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tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23),
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vde->mbe, 0x80);
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tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23),
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vde->mbe, 0x80);
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frame_idx_enb_mask |= frame_idx << (6 * (idx % 4));
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@ -128,7 +176,7 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
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value |= (idx >> 2) << 24;
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value |= frame_idx_enb_mask;
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VDE_WR(value, vde->mbe + 0x80);
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tegra_vde_writel(vde, value, vde->mbe, 0x80);
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err = tegra_vde_wait_mbe(vde);
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if (err)
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@ -143,8 +191,10 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
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static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val)
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{
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VDE_WR(0xA0000000 | (reg << 24) | (val & 0xFFFF), vde->mbe + 0x80);
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VDE_WR(0xA0000000 | ((reg + 1) << 24) | (val >> 16), vde->mbe + 0x80);
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tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF),
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vde->mbe, 0x80);
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tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16),
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vde->mbe, 0x80);
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}
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static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma)
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@ -183,7 +233,7 @@ static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma)
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static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde,
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u32 value, bool wait_dma)
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{
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VDE_WR(value, vde->bsev + ICMDQUE_WR);
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tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR);
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return tegra_vde_wait_bsev(vde, wait_dma);
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}
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@ -199,11 +249,11 @@ static void tegra_vde_setup_frameid(struct tegra_vde *vde,
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u32 value1 = frame ? ((mbs_width << 16) | mbs_height) : 0;
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u32 value2 = frame ? ((((mbs_width + 1) >> 1) << 6) | 1) : 0;
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VDE_WR(y_addr >> 8, vde->frameid + 0x000 + frameid * 4);
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VDE_WR(cb_addr >> 8, vde->frameid + 0x100 + frameid * 4);
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VDE_WR(cr_addr >> 8, vde->frameid + 0x180 + frameid * 4);
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VDE_WR(value1, vde->frameid + 0x080 + frameid * 4);
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VDE_WR(value2, vde->frameid + 0x280 + frameid * 4);
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tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4);
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tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4);
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tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4);
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tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4);
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tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4);
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}
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static void tegra_setup_frameidx(struct tegra_vde *vde,
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@ -228,8 +278,7 @@ static void tegra_vde_setup_iram_entry(struct tegra_vde *vde,
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{
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u32 *iram_tables = vde->iram;
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dev_dbg(vde->miscdev.parent, "IRAM table %u: row %u: 0x%08X 0x%08X\n",
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table, row, value1, value2);
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trace_vde_setup_iram_entry(table, row, value1, value2);
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iram_tables[0x20 * table + row * 2] = value1;
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iram_tables[0x20 * table + row * 2 + 1] = value2;
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@ -245,10 +294,7 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
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int with_later_poc_nb;
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unsigned int i, k;
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dev_dbg(vde->miscdev.parent, "DPB: Frame 0: frame_num = %d\n",
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dpb_frames[0].frame_num);
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dev_dbg(vde->miscdev.parent, "REF L0:\n");
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trace_vde_ref_l0(dpb_frames[0].frame_num);
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for (i = 0; i < 16; i++) {
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if (i < ref_frames_nb) {
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@ -260,11 +306,6 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
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value |= !(frame->flags & FLAG_B_FRAME) << 25;
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value |= 1 << 24;
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value |= frame->frame_num;
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dev_dbg(vde->miscdev.parent,
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"\tFrame %d: frame_num = %d B_frame = %d\n",
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i + 1, frame->frame_num,
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(frame->flags & FLAG_B_FRAME));
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} else {
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aux_addr = 0x6ADEAD00;
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value = 0;
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@ -284,9 +325,7 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
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with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb;
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dev_dbg(vde->miscdev.parent,
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"REF L1: with_later_poc_nb %d with_earlier_poc_nb %d\n",
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with_later_poc_nb, with_earlier_poc_nb);
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trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb);
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for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {
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frame = &dpb_frames[k + 1];
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@ -298,10 +337,6 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
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value |= 1 << 24;
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value |= frame->frame_num;
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dev_dbg(vde->miscdev.parent,
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"\tFrame %d: frame_num = %d\n",
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k + 1, frame->frame_num);
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tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
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}
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@ -315,10 +350,6 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
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value |= 1 << 24;
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value |= frame->frame_num;
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dev_dbg(vde->miscdev.parent,
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"\tFrame %d: frame_num = %d\n",
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k + 1, frame->frame_num);
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tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
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}
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}
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@ -334,32 +365,32 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
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u32 value;
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int err;
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tegra_vde_set_bits(vde, 0x000A, vde->sxe + 0xF0);
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tegra_vde_set_bits(vde, 0x000B, vde->bsev + CMDQUE_CONTROL);
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tegra_vde_set_bits(vde, 0x8002, vde->mbe + 0x50);
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tegra_vde_set_bits(vde, 0x000A, vde->mbe + 0xA0);
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tegra_vde_set_bits(vde, 0x000A, vde->ppe + 0x14);
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tegra_vde_set_bits(vde, 0x000A, vde->ppe + 0x28);
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tegra_vde_set_bits(vde, 0x0A00, vde->mce + 0x08);
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tegra_vde_set_bits(vde, 0x000A, vde->tfe + 0x00);
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tegra_vde_set_bits(vde, 0x0005, vde->vdma + 0x04);
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tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0);
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tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL);
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tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50);
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tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0);
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tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14);
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tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28);
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tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08);
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tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00);
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tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04);
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VDE_WR(0x00000000, vde->vdma + 0x1C);
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VDE_WR(0x00000000, vde->vdma + 0x00);
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VDE_WR(0x00000007, vde->vdma + 0x04);
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VDE_WR(0x00000007, vde->frameid + 0x200);
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VDE_WR(0x00000005, vde->tfe + 0x04);
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VDE_WR(0x00000000, vde->mbe + 0x84);
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VDE_WR(0x00000010, vde->sxe + 0x08);
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VDE_WR(0x00000150, vde->sxe + 0x54);
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VDE_WR(0x0000054C, vde->sxe + 0x58);
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VDE_WR(0x00000E34, vde->sxe + 0x5C);
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VDE_WR(0x063C063C, vde->mce + 0x10);
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VDE_WR(0x0003FC00, vde->bsev + INTR_STATUS);
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VDE_WR(0x0000150D, vde->bsev + BSE_CONFIG);
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VDE_WR(0x00000100, vde->bsev + BSE_INT_ENB);
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VDE_WR(0x00000000, vde->bsev + 0x98);
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VDE_WR(0x00000060, vde->bsev + 0x9C);
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tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C);
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tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00);
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tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04);
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tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200);
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tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04);
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tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);
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tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08);
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tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54);
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tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58);
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tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C);
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tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10);
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tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS);
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tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG);
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tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB);
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tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98);
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tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C);
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memset(vde->iram + 128, 0, macroblocks_nb / 2);
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@ -376,13 +407,13 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
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*/
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wmb();
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VDE_WR(0x00000000, vde->bsev + 0x8C);
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VDE_WR(bitstream_data_addr + bitstream_data_size,
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vde->bsev + 0x54);
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tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C);
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tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size,
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vde->bsev, 0x54);
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value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3;
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VDE_WR(value, vde->bsev + 0x88);
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tegra_vde_writel(vde, value, vde->bsev, 0x88);
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err = tegra_vde_wait_bsev(vde, false);
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if (err)
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@ -417,7 +448,7 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
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value |= ctx->pic_width_in_mbs << 11;
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value |= ctx->pic_height_in_mbs << 3;
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VDE_WR(value, vde->sxe + 0x10);
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tegra_vde_writel(vde, value, vde->sxe, 0x10);
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value = !ctx->baseline_profile << 17;
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value |= ctx->level_idc << 13;
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@ -425,54 +456,54 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
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value |= ctx->pic_order_cnt_type << 5;
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value |= ctx->log2_max_frame_num;
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VDE_WR(value, vde->sxe + 0x40);
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tegra_vde_writel(vde, value, vde->sxe, 0x40);
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value = ctx->pic_init_qp << 25;
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value |= !!(ctx->deblocking_filter_control_present_flag) << 2;
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value |= !!ctx->pic_order_present_flag;
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VDE_WR(value, vde->sxe + 0x44);
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tegra_vde_writel(vde, value, vde->sxe, 0x44);
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value = ctx->chroma_qp_index_offset;
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value |= ctx->num_ref_idx_l0_active_minus1 << 5;
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value |= ctx->num_ref_idx_l1_active_minus1 << 10;
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value |= !!ctx->constrained_intra_pred_flag << 15;
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VDE_WR(value, vde->sxe + 0x48);
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tegra_vde_writel(vde, value, vde->sxe, 0x48);
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value = 0x0C000000;
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value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24;
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VDE_WR(value, vde->sxe + 0x4C);
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tegra_vde_writel(vde, value, vde->sxe, 0x4C);
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value = 0x03800000;
|
||||
value |= bitstream_data_size & GENMASK(19, 15);
|
||||
|
||||
VDE_WR(value, vde->sxe + 0x68);
|
||||
tegra_vde_writel(vde, value, vde->sxe, 0x68);
|
||||
|
||||
VDE_WR(bitstream_data_addr, vde->sxe + 0x6C);
|
||||
tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C);
|
||||
|
||||
value = 0x10000005;
|
||||
value |= ctx->pic_width_in_mbs << 11;
|
||||
value |= ctx->pic_height_in_mbs << 3;
|
||||
|
||||
VDE_WR(value, vde->mbe + 0x80);
|
||||
tegra_vde_writel(vde, value, vde->mbe, 0x80);
|
||||
|
||||
value = 0x26800000;
|
||||
value |= ctx->level_idc << 4;
|
||||
value |= !ctx->baseline_profile << 1;
|
||||
value |= !!ctx->direct_8x8_inference_flag;
|
||||
|
||||
VDE_WR(value, vde->mbe + 0x80);
|
||||
tegra_vde_writel(vde, value, vde->mbe, 0x80);
|
||||
|
||||
VDE_WR(0xF4000001, vde->mbe + 0x80);
|
||||
VDE_WR(0x20000000, vde->mbe + 0x80);
|
||||
VDE_WR(0xF4000101, vde->mbe + 0x80);
|
||||
tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);
|
||||
tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);
|
||||
tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);
|
||||
|
||||
value = 0x20000000;
|
||||
value |= ctx->chroma_qp_index_offset << 8;
|
||||
|
||||
VDE_WR(value, vde->mbe + 0x80);
|
||||
tegra_vde_writel(vde, value, vde->mbe, 0x80);
|
||||
|
||||
err = tegra_vde_setup_mbe_frame_idx(vde,
|
||||
ctx->dpb_frames_nb - 1,
|
||||
|
|
@ -494,7 +525,7 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
|
|||
if (!ctx->baseline_profile)
|
||||
value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1;
|
||||
|
||||
VDE_WR(value, vde->mbe + 0x80);
|
||||
tegra_vde_writel(vde, value, vde->mbe, 0x80);
|
||||
|
||||
err = tegra_vde_wait_mbe(vde);
|
||||
if (err) {
|
||||
|
|
@ -510,8 +541,9 @@ static void tegra_vde_decode_frame(struct tegra_vde *vde,
|
|||
{
|
||||
reinit_completion(&vde->decode_completion);
|
||||
|
||||
VDE_WR(0x00000001, vde->bsev + 0x8C);
|
||||
VDE_WR(0x20000000 | (macroblocks_nb - 1), vde->sxe + 0x00);
|
||||
tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C);
|
||||
tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1),
|
||||
vde->sxe, 0x00);
|
||||
}
|
||||
|
||||
static void tegra_vde_detach_and_put_dmabuf(struct dma_buf_attachment *a,
|
||||
|
|
@ -883,8 +915,8 @@ static int tegra_vde_ioctl_decode_h264(struct tegra_vde *vde,
|
|||
timeout = wait_for_completion_interruptible_timeout(
|
||||
&vde->decode_completion, msecs_to_jiffies(1000));
|
||||
if (timeout == 0) {
|
||||
bsev_ptr = readl_relaxed(vde->bsev + 0x10);
|
||||
macroblocks_nb = readl_relaxed(vde->sxe + 0xC8) & 0x1FFF;
|
||||
bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10);
|
||||
macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF;
|
||||
read_bytes = bsev_ptr ? bsev_ptr - bitstream_data_addr : 0;
|
||||
|
||||
dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n",
|
||||
|
|
@ -962,7 +994,7 @@ static irqreturn_t tegra_vde_isr(int irq, void *data)
|
|||
if (completion_done(&vde->decode_completion))
|
||||
return IRQ_NONE;
|
||||
|
||||
tegra_vde_set_bits(vde, 0, vde->frameid + 0x208);
|
||||
tegra_vde_set_bits(vde, 0, vde->frameid, 0x208);
|
||||
complete(&vde->decode_completion);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
|
|||
93
drivers/staging/media/tegra-vde/trace.h
Normal file
93
drivers/staging/media/tegra-vde/trace.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#undef TRACE_SYSTEM
|
||||
#define TRACE_SYSTEM tegra_vde
|
||||
|
||||
#if !defined(TEGRA_VDE_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
|
||||
#define TEGRA_VDE_TRACE_H
|
||||
|
||||
#include <linux/tracepoint.h>
|
||||
|
||||
DECLARE_EVENT_CLASS(register_access,
|
||||
TP_PROTO(struct tegra_vde *vde, void __iomem *base,
|
||||
u32 offset, u32 value),
|
||||
TP_ARGS(vde, base, offset, value),
|
||||
TP_STRUCT__entry(
|
||||
__string(hw_name, tegra_vde_reg_base_name(vde, base))
|
||||
__field(u32, offset)
|
||||
__field(u32, value)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__assign_str(hw_name, tegra_vde_reg_base_name(vde, base));
|
||||
__entry->offset = offset;
|
||||
__entry->value = value;
|
||||
),
|
||||
TP_printk("%s:0x%03x 0x%08x", __get_str(hw_name), __entry->offset,
|
||||
__entry->value)
|
||||
);
|
||||
|
||||
DEFINE_EVENT(register_access, vde_writel,
|
||||
TP_PROTO(struct tegra_vde *vde, void __iomem *base,
|
||||
u32 offset, u32 value),
|
||||
TP_ARGS(vde, base, offset, value));
|
||||
DEFINE_EVENT(register_access, vde_readl,
|
||||
TP_PROTO(struct tegra_vde *vde, void __iomem *base,
|
||||
u32 offset, u32 value),
|
||||
TP_ARGS(vde, base, offset, value));
|
||||
|
||||
TRACE_EVENT(vde_setup_iram_entry,
|
||||
TP_PROTO(unsigned int table, unsigned int row, u32 value, u32 aux_addr),
|
||||
TP_ARGS(table, row, value, aux_addr),
|
||||
TP_STRUCT__entry(
|
||||
__field(unsigned int, table)
|
||||
__field(unsigned int, row)
|
||||
__field(u32, value)
|
||||
__field(u32, aux_addr)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->table = table;
|
||||
__entry->row = row;
|
||||
__entry->value = value;
|
||||
__entry->aux_addr = aux_addr;
|
||||
),
|
||||
TP_printk("[%u][%u] = { 0x%08x (flags = \"%s\", frame_num = %u); 0x%08x }",
|
||||
__entry->table, __entry->row, __entry->value,
|
||||
__print_flags(__entry->value, " ", { (1 << 25), "B" }),
|
||||
__entry->value & 0x7FFFFF, __entry->aux_addr)
|
||||
);
|
||||
|
||||
TRACE_EVENT(vde_ref_l0,
|
||||
TP_PROTO(unsigned int frame_num),
|
||||
TP_ARGS(frame_num),
|
||||
TP_STRUCT__entry(
|
||||
__field(unsigned int, frame_num)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->frame_num = frame_num;
|
||||
),
|
||||
TP_printk("REF L0: DPB: Frame 0: frame_num = %u", __entry->frame_num)
|
||||
);
|
||||
|
||||
TRACE_EVENT(vde_ref_l1,
|
||||
TP_PROTO(unsigned int with_later_poc_nb,
|
||||
unsigned int with_earlier_poc_nb),
|
||||
TP_ARGS(with_later_poc_nb, with_earlier_poc_nb),
|
||||
TP_STRUCT__entry(
|
||||
__field(unsigned int, with_later_poc_nb)
|
||||
__field(unsigned int, with_earlier_poc_nb)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->with_later_poc_nb = with_later_poc_nb;
|
||||
__entry->with_earlier_poc_nb = with_earlier_poc_nb;
|
||||
),
|
||||
TP_printk("REF L1: with_later_poc_nb %u, with_earlier_poc_nb %u",
|
||||
__entry->with_later_poc_nb, __entry->with_earlier_poc_nb)
|
||||
);
|
||||
|
||||
#endif /* TEGRA_VDE_TRACE_H */
|
||||
|
||||
/* This part must be outside protection */
|
||||
#undef TRACE_INCLUDE_PATH
|
||||
#define TRACE_INCLUDE_PATH ../../drivers/staging/media/tegra-vde
|
||||
#define TRACE_INCLUDE_FILE trace
|
||||
#include <trace/define_trace.h>
|
||||
Loading…
Reference in a new issue