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drm/bridge: tc358767: fix AUXDATAn registers access 

First four bytes should go to DP0_AUXWDATA0. Due to bug if
len > 4 first four bytes was writen to DP0_AUXWDATA1 and all
data get shifted by 4 bytes. Fix it.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1510073785-16108-6-git-send-email-andrey.gusakov@cogentembedded.com
This commit is contained in:
Andrey Gusakov 2017-11-07 19:56:23 +03:00 committed by Andrzej Hajda
parent 66d1c3b94d
commit 9217c1abbc
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/bridge/tc358767.c
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@ -318,7 +318,7 @@ static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
tmp = (tmp << 8) | buf[i];
i++;
if (((i % 4) == 0) || (i == size)) {
tc_write(DP0_AUXWDATA(i >> 2), tmp);
tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
tmp = 0;
}
}