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drm/bridge: tc358767: fix AUXDATAn registers access
First four bytes should go to DP0_AUXWDATA0. Due to bug if len > 4 first four bytes was writen to DP0_AUXWDATA1 and all data get shifted by 4 bytes. Fix it. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1510073785-16108-6-git-send-email-andrey.gusakov@cogentembedded.com
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@ -318,7 +318,7 @@ static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
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tmp = (tmp << 8) | buf[i];
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i++;
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if (((i % 4) == 0) || (i == size)) {
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tc_write(DP0_AUXWDATA(i >> 2), tmp);
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tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
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tmp = 0;
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}
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}
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