This pull request contains Broadcom ARM64-based SocS Device Tree
updates for 5.20, please pull the following: - William adds the ARCH_BCMBCA Kconfig entry to follow the ARM 32-bit counter part and adds basic support for these DSL/PON SoCs: 63158, 4912, 63146, 6856, 6813 - Anand adds basic support for the 6858 SoC - Krzysztof fixes a missing space between a property name and its value in a number of DTS files -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmLMT6AACgkQh9CWnEQH BwSmXhAAstUebP+FxQFCnCmrcpBktlXcPpAMDmTxgwKGQrHmITdAhvfK+eHpWsPo 9uBs1BdlHjyN/gC2p/o7S01WjI7j/Qodw106vgfhzIYuPbJUl/LVzYcubn1nhJvS fUvEh57Dw1jrqECy0nhUFltNf+C2Tw2R1Ug1BR2+K4ekLwU7Lmy6/4ugxbS1jSIH pWTqXNyTwzboYM4js5gPhPKTIrQHgYUd1YxFeExlG3LiLTI3WdnFwvsnHqFbmdHV 85UDR9Jic/tmWS7Egs7fqcxkHadWqSrgOE/79WKiWs/e+V8IxB4JfanEa6ltnZ6a JXiKPNryeZuhW0+LtqBgzU5I7DczH9zHVuBjaLvaLSGENf/bz9dhks9A1gQF/nkB ZgbtrMJJVHRXyGFovX7cjqtvVKSX4WUa/In2OKw8RJ51NKo5IWVnbn+R/4hA/6Tg kAYMeGLKggqeI4i77H6CXwgJTBJkidSEzw6zKJqALEPHT3nI+AqWUGN0DlFbQkko yd8Wte0cFXZ6/U3as7Ie159SoHj1k9R9XORhIOUKmoN11M7n+072h2VOQNsbVeni KiT7CVqy2FVL8HeCnAkJVNRbl+pBowtksJAUMl0zIzYpN9eGIelQJDIUXQxfXl29 Fvua4XALaIiNDWa9C+mX3DzB/UFGpYiQIutv2xVuHUH/VX8fshc= =WeA3 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLQOQMACgkQmmx57+YA GNmi0w/+N7ZE7JF2Qmlf9EDmy/rq4vfZz7ZJ4pCT30pUtC16GGbbynsKWnYB7bb0 jeXxrytfr+yFZY7P8R83GkIpkBBpbhUlSWCi5W1VTQVaZLC5KZWZtPZymt4YD8KV zrIBVBX1ZxFNCOSMh5rP6ByrbJiuiQQ2DQiPgHDZMxFH8xUPKDvAOVR8JPhtlo6Q YtQgKA4zHXDkPQied4Je/NYfrh9xyLuskDmlBZ0OYvqp3XLLCBAlNKghH0bHSvt/ KW1AvQtacfI2STD2gGWlGktUJr9ff0Qhxe2DsDauhANShNSVGlFrtqJXxFDf79ly amlqhXtZI2I2osyukm4PK3Ys1smDnBmNY7nbctCAXUTtcsKI/VUqAud79++U5xcD +BrGrZ58KcLLJTcktxszdHvvP7P92B02jhPx2Oeqe0I59hbeXO1ozglBWw0VjJj1 Iar5p+SDo6k6F7t2pjLWg4hjtljIYn8RX6yKX6xisNBKioxAxv5HAYjN0IrENCrY ZXnOMpnDhnnomY4WsEEw9KOutZ1aXDphCfJs22wPyhH0cpsM4dtD+BnR2NmWnko8 h20M3b0xQui9P1N7iDNheAjuXJbOapu/D7R80NhCo9fWKILFaRI/YBkNSkc2juUT e5fMRqLpSzoRswa12PBnbZgZcPQop7DKq3rv8cGL9jR0OTqL2nU= =9IyI -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-5.20/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM64-based SocS Device Tree updates for 5.20, please pull the following: - William adds the ARCH_BCMBCA Kconfig entry to follow the ARM 32-bit counter part and adds basic support for these DSL/PON SoCs: 63158, 4912, 63146, 6856, 6813 - Anand adds basic support for the 6858 SoC - Krzysztof fixes a missing space between a property name and its value in a number of DTS files * tag 'arm-soc/for-5.20/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: Add DTS files for bcmbca SoC BCM6813 arm64: dts: Add DTS files for bcmbca SoC BCM6856 arm64: dts: Add DTS files for bcmbca SoC BCM63146 arm64: dts: broadcom: adjust whitespace around '=' ARM64: dts: Add DTS files for bcmbca SoC BCM6858 arm64: dts: Add DTS files for bcmbca SoC BCM4912 arm64: dts: Add DTS files for bcmbca SoC BCM63158 arm64: bcmbca: add arch bcmbca machine entry Link: https://lore.kernel.org/r/20220711164451.3542127-5-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
92c336e7ae
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@ -63,6 +63,15 @@ config ARCH_BCM_IPROC
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help
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This enables support for Broadcom iProc based SoCs
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config ARCH_BCMBCA
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bool "Broadcom Broadband SoC"
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help
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Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
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BCA chipset.
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This enables support for Broadcom BCA ARM-based broadband chipsets,
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including the DSL, PON and Wireless family of chips.
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config ARCH_BERLIN
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bool "Marvell Berlin SoC Family"
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select DW_APB_ICTL
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@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
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bcm2837-rpi-zero-2-w.dtb
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subdir-y += bcm4908
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subdir-y += bcmbca
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subdir-y += northstar2
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subdir-y += stingray
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
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bcm963158.dtb \
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bcm96858.dtb \
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bcm963146.dtb \
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bcm96856.dtb \
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bcm96813.dtb
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@ -0,0 +1,128 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm4912", "brcm,bcmbca";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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B53_0: cpu@0 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_1: cpu@1 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_2: cpu@2 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x2>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_3: cpu@3 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x3>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&B53_0>, <&B53_1>,
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<&B53_2>, <&B53_3>;
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};
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clocks: clocks {
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periph_clk: periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&periph_clk>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x81000000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>,
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<0x4000 0x2000>,
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<0x6000 0x2000>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>, <&uart_clk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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@ -0,0 +1,110 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm63146", "brcm,bcmbca";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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B53_0: cpu@0 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_1: cpu@1 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&B53_0>, <&B53_1>;
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};
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clocks: clocks {
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periph_clk: periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&periph_clk>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x81000000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>,
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<0x4000 0x2000>,
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<0x6000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>, <&uart_clk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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@ -0,0 +1,128 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm63158", "brcm,bcmbca";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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B53_0: cpu@0 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_1: cpu@1 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_2: cpu@2 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x2>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_3: cpu@3 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x3>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupt-affinity = <&B53_0>, <&B53_1>,
|
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<&B53_2>, <&B53_3>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
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clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6813", "brcm,bcmbca";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
B53_0: cpu@0 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_1: cpu@1 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_2: cpu@2 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_3: cpu@3 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&B53_0>, <&B53_1>,
|
||||
<&B53_2>, <&B53_3>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6856", "brcm,bcmbca";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
B53_0: cpu@0 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_1: cpu@1 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&B53_0>, <&B53_1>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk:periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>, /* GICD */
|
||||
<0x2000 0x2000>, /* GICC */
|
||||
<0x4000 0x2000>, /* GICH */
|
||||
<0x6000 0x2000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@640 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x640 0x18>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6858", "brcm,bcmbca";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
B53_0: cpu@0 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_1: cpu@1 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_2: cpu@2 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B53_3: cpu@3 {
|
||||
compatible = "brcm,brahma-b53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&B53_0>, <&B53_1>,
|
||||
<&B53_2>, <&B53_3>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk:periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>, /* GICD */
|
||||
<0x2000 0x2000>, /* GICC */
|
||||
<0x4000 0x2000>, /* GICH */
|
||||
<0x6000 0x2000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0xff800000 0x62000>;
|
||||
|
||||
uart0: serial@640 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x640 0x18>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4912.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM94912 Reference Board";
|
||||
compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm63146.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM963146 Reference Board";
|
||||
compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm63158.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM963158 Reference Board";
|
||||
compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6813.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96813 Reference Board";
|
||||
compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6856.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96856 Reference Board";
|
||||
compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6858.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96858 Reference Board";
|
||||
compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -567,7 +567,7 @@
|
|||
reg-names = "amac_base";
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status= "disabled";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand@360000 {
|
||||
|
|
|
|||
Loading…
Reference in New Issue