mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 15:47:36 +00:00
Renesas ARM Based SoC DT Updates for v4.9
* Add DU, VIN, I2C, SDHI, EtherAVB, GPIO support to r8a7792 * Enable CAN0 on r8a7792/blanche * Enable sound on r8a7794/silk * Correct SDHI register size on r8a7794 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXsYLcAAoJENfPZGlqN0++yJoQALZslDHrmZLDWIjf4aWhF1/t AHKX5mQJ4sAAQMdFrXQxi10PdCdjrYEeTpzvTPKBozpNsvxfrGmsxgQgkoeY2/an v5KN55O4ryUHtG2sBVs0ltGjiILi4OJvEpe2jHeFTpSiGnOkMjTYCJ456+6CE81v 8XF4Mk07ho3YlJPirdWPfCrNxWM2UZzxcC68JGOzv3YbI16P4+1XvhBr26Pk0UOm biKVUOraE8THGx3zvrd+oZ0SFVn96NZwya2eF7nhwhJF5pnknCUFIFjGaYVfKNnG ffjfgpAr7wTLBBSSLZUU6MHq5CND0RAiz9J28mT/cmZsubl4VrmfmjO2sg4icevM XsIyQ9+g9Y0ge+wqb1SGgObnfXAArFNIcfvsyiZdsG5yacA4ax1AGYXMqxkNK9pv tyFeGeo5lYVp/BjIS6BDB9Rupd5DIyDSVIU70fsjlnJsDN8JyERO/qQh5g+NuVgF N+E/EByIYmQynilcMV/od6vXYWKJzq6pGE2slKx15T/KrnDglrUPKa80YEhJWIVP uBT6ooC+2JJ7M/vbqeiPKyQ4UvEYnvX/0s4HDwrcOwksP+aXSZZ/2ZIp4Fq9f7BD kEs1I/Qh2oSzo1Sj3pa5IZwISQ1N19CTPLMOfLaun0MwK0hhrXUjHYwLcq6Oqku+ 1NcspdYSViVUgHjkJky4 =YZIK -----END PGP SIGNATURE----- Merge tag 'renesas-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Renesas ARM Based SoC DT Updates for v4.9" from Simon Horman: * Add DU, VIN, I2C, SDHI, EtherAVB, GPIO support to r8a7792 * Enable CAN0 on r8a7792/blanche * Enable sound on r8a7794/silk * Correct SDHI register size on r8a7794 * tag 'renesas-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (26 commits) ARM: dts: r8a7792: add DU support ARM: dts: r8a7792: add DU clocks ARM: dts: r8a7792: fix misindented line ARM: dts: silk: add sound support ARM: dts: r8a7794: add sound support ARM: dts: r8a7794: add Audio-DMAC support ARM: dts: r8a7794: add MSTP10 clocks ARM: dts: r8a7794: add MSTP5 clocks ARM: dts: r8a7794: add audio clocks ARM: dts: r8a7792: add VIN support ARM: dts: r8a7792: add VIN clocks ARM: dts: r8a7792: add I2C support ARM: dts: r8a7792: add I2C clocks ARM: dts: r8a7792: add SDHI support ARM: dts: r8a7792: add SD clocks ARM: dts: r8a7794: Correct SDHI register size ARM: dts: blanche: add CAN0 support ARM: dts: r8a7792: add CAN support ARM: dts: r8a7792: add CAN clocks ARM: dts: r8a7792: add EtherAVB support ...
This commit is contained in:
Arnd Bergmann
commit
93329cd046
5 changed files with 933 additions and 3 deletions
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@ -50,6 +50,9 @@ ethernet@18000000 {
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reg-io-width = <4>;
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vddvario-supply = <&d3_3v>;
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vdd33a-supply = <&d3_3v>;
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pinctrl-0 = <&lan89218_pins>;
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pinctrl-names = "default";
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};
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};
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@ -57,10 +60,55 @@ &extal_clk {
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clock-frequency = <20000000>;
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};
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&can_clk {
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clock-frequency = <48000000>;
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};
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&pfc {
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif3_pins: scif3 {
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groups = "scif3_data";
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function = "scif3";
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};
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lan89218_pins: lan89218 {
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intc {
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groups = "intc_irq0";
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function = "intc";
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};
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lbsc {
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groups = "lbsc_ex_cs0";
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function = "lbsc";
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};
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};
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can0_pins: can0 {
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groups = "can0_data", "can_clk";
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function = "can0";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif3 {
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pinctrl-0 = <&scif3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -18,6 +18,21 @@ / {
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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vin0 = &vin0;
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vin1 = &vin1;
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vin2 = &vin2;
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vin3 = &vin3;
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vin4 = &vin4;
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vin5 = &vin5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -108,6 +123,179 @@ sysc: system-controller@e6180000 {
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#power-domain-cells = <1>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7792";
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reg = <0 0xe6060000 0 0x144>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 29>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 23>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 28>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio6: gpio@e6055100 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055100 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio7: gpio@e6055200 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055200 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio8: gpio@e6055300 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055300 0 0x50>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 256 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio9: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 288 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio10: gpio@e6055500 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055500 0 0x50>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 320 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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gpio11: gpio@e6055600 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,gpio-rcar";
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reg = <0 0xe6055600 0 0x50>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 352 30>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7792",
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"renesas,rcar-dmac";
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@ -262,6 +450,18 @@ hscif1: serial@e62c8000 {
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status = "disabled";
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};
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sdhi0: sd@ee100000 {
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compatible = "renesas,sdhi-r8a7792";
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reg = <0 0xee100000 0 0x328>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
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<&dmac1 0xcd>, <&dmac1 0xce>;
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dma-names = "tx", "rx", "tx", "rx";
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clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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jpu: jpeg-codec@fe980000 {
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compatible = "renesas,jpu-r8a7792",
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"renesas,rcar-gen2-jpu";
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@ -271,6 +471,203 @@ jpu: jpeg-codec@fe980000 {
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a7792",
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"renesas,etheravb-rcar-gen2";
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reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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/* I2C doesn't need pinmux */
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i2c0: i2c@e6508000 {
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compatible = "renesas,i2c-r8a7792";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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compatible = "renesas,i2c-r8a7792";
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reg = <0 0xe6518000 0 0x40>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
|
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};
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i2c2: i2c@e6530000 {
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compatible = "renesas,i2c-r8a7792";
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reg = <0 0xe6530000 0 0x40>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
|
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e6540000 {
|
||||
compatible = "renesas,i2c-r8a7792";
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@e6520000 {
|
||||
compatible = "renesas,i2c-r8a7792";
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@e6528000 {
|
||||
compatible = "renesas,i2c-r8a7792";
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7792";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
reg-names = "du";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7792_CLK_DU0>,
|
||||
<&mstp7_clks R8A7792_CLK_DU1>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb0: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_rgb1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
|
||||
<&rcan_clk>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
|
||||
<&rcan_clk>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7792-cpg-clocks",
|
||||
|
|
@ -291,6 +688,13 @@ pll1_div2_clk: pll1_div2 {
|
|||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
zx_clk: zx {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
zs_clk: zs {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
|
||||
|
|
@ -298,6 +702,13 @@ zs_clk: zs {
|
|||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
hp_clk: hp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
p_clk: p {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
|
||||
|
|
@ -319,6 +730,27 @@ m2_clk: m2 {
|
|||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
sd_clk: sd {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
rcan_clk: rcan {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <49>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
zg_clk: zg {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <5>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
mstp1_clks: mstp1_clks@e6150134 {
|
||||
|
|
@ -341,6 +773,15 @@ R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
|
|||
>;
|
||||
clock-output-names = "sys-dmac1", "sys-dmac0";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7792-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&sd_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7792_CLK_SDHI0>;
|
||||
clock-output-names = "sdhi0";
|
||||
};
|
||||
mstp4_clks: mstp4_clks@e6150140 {
|
||||
compatible = "renesas,r8a7792-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
|
|
@ -355,15 +796,62 @@ mstp7_clks: mstp7_clks@e615014c {
|
|||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
||||
clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
|
||||
<&p_clk>, <&p_clk>;
|
||||
<&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
|
||||
R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
|
||||
R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
|
||||
R8A7792_CLK_DU1 R8A7792_CLK_DU0
|
||||
>;
|
||||
clock-output-names = "hscif1", "hscif0", "scif3",
|
||||
"scif2", "scif1", "scif0";
|
||||
"scif2", "scif1", "scif0",
|
||||
"du1", "du0";
|
||||
};
|
||||
mstp8_clks: mstp8_clks@e6150990 {
|
||||
compatible = "renesas,r8a7792-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
||||
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
|
||||
<&zg_clk>, <&zg_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
|
||||
R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
|
||||
R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
|
||||
R8A7792_CLK_ETHERAVB
|
||||
>;
|
||||
clock-output-names = "vin5", "vin4", "vin3", "vin2",
|
||||
"vin1", "vin0", "etheravb";
|
||||
};
|
||||
mstp9_clks: mstp9_clks@e6150994 {
|
||||
compatible = "renesas,r8a7792-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
||||
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
|
||||
R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
|
||||
R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
|
||||
R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
|
||||
R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
|
||||
R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
|
||||
R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
|
||||
R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
|
||||
R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
|
||||
R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
|
||||
>;
|
||||
clock-output-names =
|
||||
"gpio7", "gpio6", "gpio5", "gpio4",
|
||||
"gpio3", "gpio2", "gpio1", "gpio0",
|
||||
"gpio11", "gpio10", "can1", "can0",
|
||||
"gpio9", "gpio8", "i2c5", "i2c4",
|
||||
"i2c3", "i2c2", "i2c1", "i2c0";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -382,4 +870,12 @@ scif_clk: scif {
|
|||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,17 @@
|
|||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 2-1: AK4643
|
||||
* 2-3: ADV7511
|
||||
*
|
||||
* This command is required before playback/capture:
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7794.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -119,6 +130,29 @@ x3_clk: x3-clock {
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x9_clk: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&soundcodec>;
|
||||
simple-audio-card,frame-master = <&soundcodec>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
soundcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&x9_clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
|
|
@ -193,6 +227,16 @@ du1_pins: du1 {
|
|||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
|
||||
function = "du1";
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
audio_clk_pins: audio_clk {
|
||||
groups = "audio_clkc";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
|
|
@ -230,6 +274,12 @@ &i2c1 {
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
|
|
@ -392,3 +442,23 @@ endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0>;
|
||||
capture = <&ssi1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -296,6 +296,34 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
|||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
|
||||
reg = <0 0xec700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
|
||||
"ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
||||
scifa0: serial@e6c40000 {
|
||||
compatible = "renesas,scifa-r8a7794",
|
||||
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||
|
|
@ -697,7 +725,7 @@ mmcif0: mmc@ee200000 {
|
|||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7794";
|
||||
reg = <0 0xee100000 0 0x200>;
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
||||
|
|
@ -952,6 +980,27 @@ scif_clk: scif {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed
|
||||
* frequency clocks by default. Boards that provide audio
|
||||
* clocks should override them.
|
||||
*/
|
||||
audio_clka: audio_clka {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
audio_clkb: audio_clkb {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
audio_clkc: audio_clkc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7794-cpg-clocks",
|
||||
|
|
@ -1183,6 +1232,15 @@ mstp4_clks: mstp4_clks@e6150140 {
|
|||
clock-indices = <R8A7794_CLK_IRQC>;
|
||||
clock-output-names = "irqc";
|
||||
};
|
||||
mstp5_clks: mstp5_clks@e6150144 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
||||
clocks = <&hp_clk>, <&extal_clk>, <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <R8A7794_CLK_AUDIO_DMAC0
|
||||
R8A7794_CLK_PWM>;
|
||||
clock-output-names = "audmac0", "pwm";
|
||||
};
|
||||
mstp7_clks: mstp7_clks@e615014c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
||||
|
|
@ -1237,6 +1295,58 @@ R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
|
|||
"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
|
||||
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
|
||||
};
|
||||
mstp10_clks: mstp10_clks@e6150998 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
|
||||
clocks = <&p_clk>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&p_clk>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_ALL>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <R8A7794_CLK_SSI_ALL
|
||||
R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
|
||||
R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
|
||||
R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
|
||||
R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
|
||||
R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
|
||||
R8A7794_CLK_SCU_ALL
|
||||
R8A7794_CLK_SCU_DVC1
|
||||
R8A7794_CLK_SCU_DVC0
|
||||
R8A7794_CLK_SCU_CTU1_MIX1
|
||||
R8A7794_CLK_SCU_CTU0_MIX0
|
||||
R8A7794_CLK_SCU_SRC6
|
||||
R8A7794_CLK_SCU_SRC5
|
||||
R8A7794_CLK_SCU_SRC4
|
||||
R8A7794_CLK_SCU_SRC3
|
||||
R8A7794_CLK_SCU_SRC2
|
||||
R8A7794_CLK_SCU_SRC1>;
|
||||
clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
|
||||
"ssi6", "ssi5", "ssi4", "ssi3",
|
||||
"ssi2", "ssi1", "ssi0",
|
||||
"scu-all", "scu-dvc1", "scu-dvc0",
|
||||
"scu-ctu1-mix1", "scu-ctu0-mix0",
|
||||
"scu-src6", "scu-src5", "scu-src4",
|
||||
"scu-src3", "scu-src2", "scu-src1";
|
||||
};
|
||||
mstp11_clks: mstp11_clks@e615099c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
||||
|
|
@ -1306,4 +1416,185 @@ ipmmu_gp: mmu@e62a0000 {
|
|||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
*
|
||||
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
||||
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a7794",
|
||||
"renesas,rcar_sound-gen2";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI9>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI8>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI7>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI6>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI5>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI4>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI3>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI2>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI1>,
|
||||
<&mstp10_clks R8A7794_CLK_SSI0>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_SRC6>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_SRC5>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_SRC4>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_SRC3>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_SRC2>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_SRC1>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_DVC0>,
|
||||
<&mstp10_clks R8A7794_CLK_SCU_DVC1>,
|
||||
<&audio_clka>, <&audio_clkb>, <&audio_clkc>,
|
||||
<&m2_clk>;
|
||||
clock-names = "ssi-all",
|
||||
"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
|
||||
"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
|
||||
"src.6", "src.5", "src.4", "src.3", "src.2",
|
||||
"src.1",
|
||||
"ctu.0", "ctu.1",
|
||||
"mix.0", "mix.1",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
rcar_sound,dvc {
|
||||
dvc0: dvc@0 {
|
||||
dmas = <&audma0 0xbc>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
dvc1: dvc@1 {
|
||||
dmas = <&audma0 0xbe>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,mix {
|
||||
mix0: mix@0 { };
|
||||
mix1: mix@1 { };
|
||||
};
|
||||
|
||||
rcar_sound,ctu {
|
||||
ctu00: ctu@0 { };
|
||||
ctu01: ctu@1 { };
|
||||
ctu02: ctu@2 { };
|
||||
ctu03: ctu@3 { };
|
||||
ctu10: ctu@4 { };
|
||||
ctu11: ctu@5 { };
|
||||
ctu12: ctu@6 { };
|
||||
ctu13: ctu@7 { };
|
||||
};
|
||||
|
||||
rcar_sound,src {
|
||||
src@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
src1: src@1 {
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x87>, <&audma0 0x9c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src2: src@2 {
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x89>, <&audma0 0x9e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src3: src@3 {
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8b>, <&audma0 0xa0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src4: src@4 {
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8d>, <&audma0 0xb0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src5: src@5 {
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src6: src@6 {
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x91>, <&audma0 0xb4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi@0 {
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x01>, <&audma0 0x02>,
|
||||
<&audma0 0x15>, <&audma0 0x16>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi1: ssi@1 {
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x03>, <&audma0 0x04>,
|
||||
<&audma0 0x49>, <&audma0 0x4a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi2: ssi@2 {
|
||||
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x05>, <&audma0 0x06>,
|
||||
<&audma0 0x63>, <&audma0 0x64>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi3: ssi@3 {
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma0 0x08>,
|
||||
<&audma0 0x6f>, <&audma0 0x70>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi4: ssi@4 {
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma0 0x0a>,
|
||||
<&audma0 0x71>, <&audma0 0x72>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi5: ssi@5 {
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0b>, <&audma0 0x0c>,
|
||||
<&audma0 0x73>, <&audma0 0x74>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi6: ssi@6 {
|
||||
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0d>, <&audma0 0x0e>,
|
||||
<&audma0 0x75>, <&audma0 0x76>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi7: ssi@7 {
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0f>, <&audma0 0x10>,
|
||||
<&audma0 0x79>, <&audma0 0x7a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi8: ssi@8 {
|
||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x11>, <&audma0 0x12>,
|
||||
<&audma0 0x7b>, <&audma0 0x7c>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi9: ssi@9 {
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x13>, <&audma0 0x14>,
|
||||
<&audma0 0x7d>, <&audma0 0x7e>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@
|
|||
#define R8A7794_CLK_IRQC 7
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7794_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7794_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
|
|
@ -107,6 +108,30 @@
|
|||
#define R8A7794_CLK_I2C1 30
|
||||
#define R8A7794_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7794_CLK_SSI_ALL 5
|
||||
#define R8A7794_CLK_SSI9 6
|
||||
#define R8A7794_CLK_SSI8 7
|
||||
#define R8A7794_CLK_SSI7 8
|
||||
#define R8A7794_CLK_SSI6 9
|
||||
#define R8A7794_CLK_SSI5 10
|
||||
#define R8A7794_CLK_SSI4 11
|
||||
#define R8A7794_CLK_SSI3 12
|
||||
#define R8A7794_CLK_SSI2 13
|
||||
#define R8A7794_CLK_SSI1 14
|
||||
#define R8A7794_CLK_SSI0 15
|
||||
#define R8A7794_CLK_SCU_ALL 17
|
||||
#define R8A7794_CLK_SCU_DVC1 18
|
||||
#define R8A7794_CLK_SCU_DVC0 19
|
||||
#define R8A7794_CLK_SCU_CTU1_MIX1 20
|
||||
#define R8A7794_CLK_SCU_CTU0_MIX0 21
|
||||
#define R8A7794_CLK_SCU_SRC6 25
|
||||
#define R8A7794_CLK_SCU_SRC5 26
|
||||
#define R8A7794_CLK_SCU_SRC4 27
|
||||
#define R8A7794_CLK_SCU_SRC3 28
|
||||
#define R8A7794_CLK_SCU_SRC2 29
|
||||
#define R8A7794_CLK_SCU_SRC1 30
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7794_CLK_SCIFA3 6
|
||||
#define R8A7794_CLK_SCIFA4 7
|
||||
|
|
|
|||
Loading…
Reference in a new issue