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scsi: ufs: Fix irq return code
Return IRQ_HANDLED only if the irq is really handled, this will help in catching spurious interrupts that go unhandled. Link: https://lore.kernel.org/r/1573798172-20534-6-git-send-email-cang@codeaurora.org Reviewed-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by: Can Guo <cang@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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cddaebaf3d
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9333d77573
2 changed files with 100 additions and 36 deletions
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@ -240,7 +240,7 @@ static struct ufs_dev_fix ufs_fixups[] = {
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END_FIX
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};
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static void ufshcd_tmc_handler(struct ufs_hba *hba);
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static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
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static void ufshcd_async_scan(void *data, async_cookie_t cookie);
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static int ufshcd_reset_and_restore(struct ufs_hba *hba);
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static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
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@ -4799,19 +4799,29 @@ ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
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* ufshcd_uic_cmd_compl - handle completion of uic command
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* @hba: per adapter instance
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* @intr_status: interrupt status generated by the controller
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*
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
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static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
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{
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irqreturn_t retval = IRQ_NONE;
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if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
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hba->active_uic_cmd->argument2 |=
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ufshcd_get_uic_cmd_result(hba);
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hba->active_uic_cmd->argument3 =
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ufshcd_get_dme_attr_val(hba);
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complete(&hba->active_uic_cmd->done);
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retval = IRQ_HANDLED;
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}
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if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
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if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
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complete(hba->uic_async_done);
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retval = IRQ_HANDLED;
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}
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return retval;
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}
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/**
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@ -4867,8 +4877,12 @@ static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
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/**
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* ufshcd_transfer_req_compl - handle SCSI and query command completion
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* @hba: per adapter instance
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*
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
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static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
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{
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unsigned long completed_reqs;
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u32 tr_doorbell;
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@ -4887,7 +4901,12 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
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tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
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completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
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__ufshcd_transfer_req_compl(hba, completed_reqs);
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if (completed_reqs) {
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__ufshcd_transfer_req_compl(hba, completed_reqs);
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return IRQ_HANDLED;
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} else {
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return IRQ_NONE;
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}
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}
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/**
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@ -5406,61 +5425,77 @@ static void ufshcd_err_handler(struct work_struct *work)
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/**
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* ufshcd_update_uic_error - check and set fatal UIC error flags.
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* @hba: per-adapter instance
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*
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static void ufshcd_update_uic_error(struct ufs_hba *hba)
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static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
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{
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u32 reg;
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irqreturn_t retval = IRQ_NONE;
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/* PHY layer lane error */
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reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
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/* Ignore LINERESET indication, as this is not an error */
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if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
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(reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
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(reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
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/*
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* To know whether this error is fatal or not, DB timeout
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* must be checked but this error is handled separately.
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*/
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dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
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ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
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retval |= IRQ_HANDLED;
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}
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/* PA_INIT_ERROR is fatal and needs UIC reset */
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reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
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if (reg)
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if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
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(reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
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ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
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if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
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hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
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else if (hba->dev_quirks &
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UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
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if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
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hba->uic_error |=
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UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
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else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
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hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
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if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
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hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
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else if (hba->dev_quirks &
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UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
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if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
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hba->uic_error |=
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UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
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else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
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hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
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}
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retval |= IRQ_HANDLED;
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}
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/* UIC NL/TL/DME errors needs software retry */
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reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
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if (reg) {
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if ((reg & UIC_NETWORK_LAYER_ERROR) &&
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(reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
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ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
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hba->uic_error |= UFSHCD_UIC_NL_ERROR;
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retval |= IRQ_HANDLED;
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}
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reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
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if (reg) {
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if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
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(reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
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ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
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hba->uic_error |= UFSHCD_UIC_TL_ERROR;
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retval |= IRQ_HANDLED;
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}
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reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
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if (reg) {
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if ((reg & UIC_DME_ERROR) &&
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(reg & UIC_DME_ERROR_CODE_MASK)) {
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ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
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hba->uic_error |= UFSHCD_UIC_DME_ERROR;
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retval |= IRQ_HANDLED;
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}
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dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
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__func__, hba->uic_error);
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return retval;
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}
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static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
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@ -5483,10 +5518,15 @@ static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
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/**
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* ufshcd_check_errors - Check for errors that need s/w attention
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* @hba: per-adapter instance
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*
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static void ufshcd_check_errors(struct ufs_hba *hba)
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static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
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{
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bool queue_eh_work = false;
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irqreturn_t retval = IRQ_NONE;
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if (hba->errors & INT_FATAL_ERRORS) {
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ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
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@ -5495,7 +5535,7 @@ static void ufshcd_check_errors(struct ufs_hba *hba)
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if (hba->errors & UIC_ERROR) {
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hba->uic_error = 0;
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ufshcd_update_uic_error(hba);
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retval = ufshcd_update_uic_error(hba);
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if (hba->uic_error)
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queue_eh_work = true;
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}
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@ -5543,6 +5583,7 @@ static void ufshcd_check_errors(struct ufs_hba *hba)
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}
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schedule_work(&hba->eh_work);
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}
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retval |= IRQ_HANDLED;
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}
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/*
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* if (!queue_eh_work) -
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@ -5550,44 +5591,62 @@ static void ufshcd_check_errors(struct ufs_hba *hba)
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* itself without s/w intervention or errors that will be
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* handled by the SCSI core layer.
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*/
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return retval;
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}
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/**
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* ufshcd_tmc_handler - handle task management function completion
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* @hba: per adapter instance
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*
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static void ufshcd_tmc_handler(struct ufs_hba *hba)
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static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
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{
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u32 tm_doorbell;
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tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
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hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
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wake_up(&hba->tm_wq);
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if (hba->tm_condition) {
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wake_up(&hba->tm_wq);
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return IRQ_HANDLED;
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} else {
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return IRQ_NONE;
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}
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}
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/**
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* ufshcd_sl_intr - Interrupt service routine
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* @hba: per adapter instance
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* @intr_status: contains interrupts generated by the controller
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*
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
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static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
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{
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irqreturn_t retval = IRQ_NONE;
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hba->errors = UFSHCD_ERROR_MASK & intr_status;
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if (ufshcd_is_auto_hibern8_error(hba, intr_status))
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hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
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if (hba->errors)
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ufshcd_check_errors(hba);
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retval |= ufshcd_check_errors(hba);
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if (intr_status & UFSHCD_UIC_MASK)
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ufshcd_uic_cmd_compl(hba, intr_status);
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retval |= ufshcd_uic_cmd_compl(hba, intr_status);
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if (intr_status & UTP_TASK_REQ_COMPL)
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ufshcd_tmc_handler(hba);
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retval |= ufshcd_tmc_handler(hba);
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if (intr_status & UTP_TRANSFER_REQ_COMPL)
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ufshcd_transfer_req_compl(hba);
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retval |= ufshcd_transfer_req_compl(hba);
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return retval;
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}
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/**
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@ -5595,8 +5654,9 @@ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
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* @irq: irq number
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* @__hba: pointer to adapter instance
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*
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* Returns IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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* Returns
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* IRQ_HANDLED - If interrupt is valid
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* IRQ_NONE - If invalid interrupt
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*/
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static irqreturn_t ufshcd_intr(int irq, void *__hba)
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{
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@ -5619,14 +5679,18 @@ static irqreturn_t ufshcd_intr(int irq, void *__hba)
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intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
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if (intr_status)
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ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
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if (enabled_intr_status) {
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ufshcd_sl_intr(hba, enabled_intr_status);
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retval = IRQ_HANDLED;
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}
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if (enabled_intr_status)
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retval |= ufshcd_sl_intr(hba, enabled_intr_status);
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intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
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} while (intr_status && --retries);
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if (retval == IRQ_NONE) {
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dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n",
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__func__, intr_status);
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ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
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}
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spin_unlock(hba->host->host_lock);
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return retval;
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}
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@ -195,7 +195,7 @@ enum {
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/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
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#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
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#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
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#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
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#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
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#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
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#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
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