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crypto: qat - rename and relocate GEN2 config function
Rename qat_crypto_dev_config() in adf_gen2_dev_config() and relocate it to the newly created file adf_gen2_config.c. This function is specific to QAT GEN2 devices and will be used also to configure the compression service. In addition change the drivers to use the dev_config() in the hardware data structure (which for GEN2 devices now points to adf_gen2_dev_config()), for consistency. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
79d8dbf155
commit
93b2f5799c
14 changed files with 158 additions and 123 deletions
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@ -2,6 +2,7 @@
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/* Copyright(c) 2014 - 2021 Intel Corporation */
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/* Copyright(c) 2014 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_config.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_gen2_pfvf.h>
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#include "adf_c3xxx_hw_data.h"
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#include "adf_c3xxx_hw_data.h"
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@ -124,6 +125,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
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hw_data->reset_device = adf_reset_flr;
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hw_data->reset_device = adf_reset_flr;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->dev_config = adf_gen2_dev_config;
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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@ -201,7 +201,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto out_err_disable_aer;
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goto out_err_disable_aer;
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}
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}
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ret = qat_crypto_dev_config(accel_dev);
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ret = hw_data->dev_config(accel_dev);
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if (ret)
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if (ret)
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goto out_err_disable_aer;
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goto out_err_disable_aer;
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@ -2,6 +2,7 @@
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/* Copyright(c) 2015 - 2021 Intel Corporation */
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/* Copyright(c) 2015 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_config.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_pfvf_vf_msg.h>
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#include <adf_pfvf_vf_msg.h>
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@ -86,6 +87,7 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
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hw_data->get_sku = get_sku;
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hw_data->get_sku = get_sku;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->dev_class->instances++;
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hw_data->dev_class->instances++;
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hw_data->dev_config = adf_gen2_dev_config;
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adf_devmgr_update_class_index(hw_data);
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adf_devmgr_update_class_index(hw_data);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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@ -2,6 +2,7 @@
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/* Copyright(c) 2014 - 2021 Intel Corporation */
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/* Copyright(c) 2014 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_config.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_gen2_pfvf.h>
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#include "adf_c62x_hw_data.h"
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#include "adf_c62x_hw_data.h"
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@ -126,6 +127,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
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hw_data->reset_device = adf_reset_flr;
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hw_data->reset_device = adf_reset_flr;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->dev_config = adf_gen2_dev_config;
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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@ -201,7 +201,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto out_err_disable_aer;
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goto out_err_disable_aer;
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}
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}
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ret = qat_crypto_dev_config(accel_dev);
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ret = hw_data->dev_config(accel_dev);
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if (ret)
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if (ret)
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goto out_err_disable_aer;
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goto out_err_disable_aer;
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@ -2,6 +2,7 @@
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/* Copyright(c) 2015 - 2021 Intel Corporation */
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/* Copyright(c) 2015 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_config.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_pfvf_vf_msg.h>
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#include <adf_pfvf_vf_msg.h>
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@ -86,6 +87,7 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
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hw_data->get_sku = get_sku;
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hw_data->get_sku = get_sku;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->dev_class->instances++;
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hw_data->dev_class->instances++;
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hw_data->dev_config = adf_gen2_dev_config;
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adf_devmgr_update_class_index(hw_data);
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adf_devmgr_update_class_index(hw_data);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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@ -12,6 +12,7 @@ intel_qat-objs := adf_cfg.o \
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adf_hw_arbiter.o \
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adf_hw_arbiter.o \
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adf_sysfs.o \
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adf_sysfs.o \
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adf_gen2_hw_data.o \
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adf_gen2_hw_data.o \
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adf_gen2_config.o \
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adf_gen4_hw_data.o \
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adf_gen4_hw_data.o \
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adf_gen4_pm.o \
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adf_gen4_pm.o \
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qat_crypto.o \
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qat_crypto.o \
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@ -110,7 +110,6 @@ int adf_init_etr_data(struct adf_accel_dev *accel_dev);
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void adf_cleanup_etr_data(struct adf_accel_dev *accel_dev);
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void adf_cleanup_etr_data(struct adf_accel_dev *accel_dev);
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int qat_crypto_register(void);
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int qat_crypto_register(void);
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int qat_crypto_unregister(void);
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int qat_crypto_unregister(void);
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int qat_crypto_dev_config(struct adf_accel_dev *accel_dev);
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int qat_crypto_vf_dev_config(struct adf_accel_dev *accel_dev);
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int qat_crypto_vf_dev_config(struct adf_accel_dev *accel_dev);
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struct qat_crypto_instance *qat_crypto_get_instance_node(int node);
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struct qat_crypto_instance *qat_crypto_get_instance_node(int node);
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void qat_crypto_put_instance(struct qat_crypto_instance *inst);
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void qat_crypto_put_instance(struct qat_crypto_instance *inst);
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131
drivers/crypto/qat/qat_common/adf_gen2_config.c
Normal file
131
drivers/crypto/qat/qat_common/adf_gen2_config.c
Normal file
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@ -0,0 +1,131 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation */
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#include "adf_accel_devices.h"
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#include "adf_cfg.h"
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#include "adf_cfg_strings.h"
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#include "adf_gen2_config.h"
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#include "adf_common_drv.h"
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#include "qat_crypto.h"
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#include "adf_transport_access_macros.h"
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static int adf_gen2_crypto_dev_config(struct adf_accel_dev *accel_dev)
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{
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char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
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int banks = GET_MAX_BANKS(accel_dev);
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int cpus = num_online_cpus();
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unsigned long val;
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int instances;
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int ret;
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int i;
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if (adf_hw_dev_has_crypto(accel_dev))
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instances = min(cpus, banks);
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else
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instances = 0;
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ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
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if (ret)
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goto err;
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ret = adf_cfg_section_add(accel_dev, "Accelerator0");
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if (ret)
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goto err;
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for (i = 0; i < instances; i++) {
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val = i;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_BANK_NUM, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_ETRMGR_CORE_AFFINITY,
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i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_SIZE, i);
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val = 128;
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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val = 512;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_SIZE, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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val = 0;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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val = 2;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_TX, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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val = 8;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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val = 10;
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snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_RX, i);
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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val = ADF_COALESCING_DEF_TIME;
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snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
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ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
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key, &val, ADF_DEC);
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if (ret)
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goto err;
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}
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val = i;
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ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
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&val, ADF_DEC);
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if (ret)
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goto err;
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set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
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return 0;
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err:
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dev_err(&GET_DEV(accel_dev), "Failed to start QAT accel dev\n");
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return ret;
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}
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/**
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* adf_gen2_dev_config() - create dev config required to create instances
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*
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* @accel_dev: Pointer to acceleration device.
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*
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* Function creates device configuration required to create instances
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*
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* Return: 0 on success, error code otherwise.
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*/
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int adf_gen2_dev_config(struct adf_accel_dev *accel_dev)
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{
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return adf_gen2_crypto_dev_config(accel_dev);
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}
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EXPORT_SYMBOL_GPL(adf_gen2_dev_config);
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10
drivers/crypto/qat/qat_common/adf_gen2_config.h
Normal file
10
drivers/crypto/qat/qat_common/adf_gen2_config.h
Normal file
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@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2022 Intel Corporation */
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#ifndef ADF_GEN2_CONFIG_H_
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#define ADF_GEN2_CONFIG_H_
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#include "adf_accel_devices.h"
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int adf_gen2_dev_config(struct adf_accel_dev *accel_dev);
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#endif
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@ -5,7 +5,6 @@
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#include "adf_accel_devices.h"
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#include "adf_accel_devices.h"
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#include "adf_common_drv.h"
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#include "adf_common_drv.h"
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#include "adf_transport.h"
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#include "adf_transport.h"
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#include "adf_transport_access_macros.h"
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#include "adf_cfg.h"
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#include "adf_cfg.h"
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#include "adf_cfg_strings.h"
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#include "adf_cfg_strings.h"
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#include "adf_gen2_hw_data.h"
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#include "adf_gen2_hw_data.h"
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@ -126,126 +125,9 @@ int qat_crypto_vf_dev_config(struct adf_accel_dev *accel_dev)
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return -EFAULT;
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return -EFAULT;
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}
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}
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return qat_crypto_dev_config(accel_dev);
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return GET_HW_DATA(accel_dev)->dev_config(accel_dev);
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}
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}
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/**
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* qat_crypto_dev_config() - create dev config required to create crypto inst.
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*
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* @accel_dev: Pointer to acceleration device.
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*
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* Function creates device configuration required to create crypto instances
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*
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|
||||||
* Return: 0 on success, error code otherwise.
|
|
||||||
*/
|
|
||||||
int qat_crypto_dev_config(struct adf_accel_dev *accel_dev)
|
|
||||||
{
|
|
||||||
char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
|
|
||||||
int banks = GET_MAX_BANKS(accel_dev);
|
|
||||||
int cpus = num_online_cpus();
|
|
||||||
unsigned long val;
|
|
||||||
int instances;
|
|
||||||
int ret;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (adf_hw_dev_has_crypto(accel_dev))
|
|
||||||
instances = min(cpus, banks);
|
|
||||||
else
|
|
||||||
instances = 0;
|
|
||||||
|
|
||||||
ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
ret = adf_cfg_section_add(accel_dev, "Accelerator0");
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
for (i = 0; i < instances; i++) {
|
|
||||||
val = i;
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_BANK_NUM, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_ETRMGR_CORE_AFFINITY,
|
|
||||||
i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_SIZE, i);
|
|
||||||
val = 128;
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
val = 512;
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_SIZE, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
val = 0;
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
val = 2;
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_TX, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
val = 8;
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
val = 10;
|
|
||||||
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_RX, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
val = ADF_COALESCING_DEF_TIME;
|
|
||||||
snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
|
|
||||||
key, &val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
val = i;
|
|
||||||
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
|
|
||||||
&val, ADF_DEC);
|
|
||||||
if (ret)
|
|
||||||
goto err;
|
|
||||||
|
|
||||||
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
dev_err(&GET_DEV(accel_dev), "Failed to start QAT accel dev\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL_GPL(qat_crypto_dev_config);
|
|
||||||
|
|
||||||
static int qat_crypto_create_instances(struct adf_accel_dev *accel_dev)
|
static int qat_crypto_create_instances(struct adf_accel_dev *accel_dev)
|
||||||
{
|
{
|
||||||
unsigned long num_inst, num_msg_sym, num_msg_asym;
|
unsigned long num_inst, num_msg_sym, num_msg_asym;
|
||||||
|
|
|
@ -2,6 +2,7 @@
|
||||||
/* Copyright(c) 2014 - 2021 Intel Corporation */
|
/* Copyright(c) 2014 - 2021 Intel Corporation */
|
||||||
#include <adf_accel_devices.h>
|
#include <adf_accel_devices.h>
|
||||||
#include <adf_common_drv.h>
|
#include <adf_common_drv.h>
|
||||||
|
#include <adf_gen2_config.h>
|
||||||
#include <adf_gen2_hw_data.h>
|
#include <adf_gen2_hw_data.h>
|
||||||
#include <adf_gen2_pfvf.h>
|
#include <adf_gen2_pfvf.h>
|
||||||
#include "adf_dh895xcc_hw_data.h"
|
#include "adf_dh895xcc_hw_data.h"
|
||||||
|
@ -234,6 +235,7 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
|
||||||
hw_data->enable_ints = adf_gen2_enable_ints;
|
hw_data->enable_ints = adf_gen2_enable_ints;
|
||||||
hw_data->reset_device = adf_reset_sbr;
|
hw_data->reset_device = adf_reset_sbr;
|
||||||
hw_data->disable_iov = adf_disable_sriov;
|
hw_data->disable_iov = adf_disable_sriov;
|
||||||
|
hw_data->dev_config = adf_gen2_dev_config;
|
||||||
|
|
||||||
adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
|
adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
|
||||||
hw_data->pfvf_ops.enable_vf2pf_interrupts = enable_vf2pf_interrupts;
|
hw_data->pfvf_ops.enable_vf2pf_interrupts = enable_vf2pf_interrupts;
|
||||||
|
|
|
@ -201,7 +201,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||||
goto out_err_disable_aer;
|
goto out_err_disable_aer;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = qat_crypto_dev_config(accel_dev);
|
ret = hw_data->dev_config(accel_dev);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto out_err_disable_aer;
|
goto out_err_disable_aer;
|
||||||
|
|
||||||
|
|
|
@ -2,6 +2,7 @@
|
||||||
/* Copyright(c) 2015 - 2021 Intel Corporation */
|
/* Copyright(c) 2015 - 2021 Intel Corporation */
|
||||||
#include <adf_accel_devices.h>
|
#include <adf_accel_devices.h>
|
||||||
#include <adf_common_drv.h>
|
#include <adf_common_drv.h>
|
||||||
|
#include <adf_gen2_config.h>
|
||||||
#include <adf_gen2_hw_data.h>
|
#include <adf_gen2_hw_data.h>
|
||||||
#include <adf_gen2_pfvf.h>
|
#include <adf_gen2_pfvf.h>
|
||||||
#include <adf_pfvf_vf_msg.h>
|
#include <adf_pfvf_vf_msg.h>
|
||||||
|
@ -86,6 +87,7 @@ void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)
|
||||||
hw_data->get_sku = get_sku;
|
hw_data->get_sku = get_sku;
|
||||||
hw_data->enable_ints = adf_vf_void_noop;
|
hw_data->enable_ints = adf_vf_void_noop;
|
||||||
hw_data->dev_class->instances++;
|
hw_data->dev_class->instances++;
|
||||||
|
hw_data->dev_config = adf_gen2_dev_config;
|
||||||
adf_devmgr_update_class_index(hw_data);
|
adf_devmgr_update_class_index(hw_data);
|
||||||
adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
|
adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
|
||||||
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
|
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
|
||||||
|
|
Loading…
Reference in a new issue