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arm64: dts: renesas: Add R-Car S4 Starter Kit support

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Add initial support for the R-Car S4 Starter Kit with R8A779F4
SoC support.  Based on a patch in the BSP.

Signed-off-by: Michael Dege <michael.dege@renesas.com>
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Co-developed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87pm1wfn8z.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto 2023-10-03 02:33:49 +00:00 committed by Geert Uytterhoeven
parent 92c4f31406
commit 93be50c7ff
2 changed files with 241 additions and 0 deletions
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1
arch/arm64/boot/dts/renesas/Makefile
View file

@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo

240
arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts Normal file
View file

@ -0,0 +1,240 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the R-Car S4 Starter Kit board
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "r8a779f4.dtsi"
/ {
model = "R-Car S4 Starter Kit board";
compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0";
aliases {
serial0 = &hscif0;
serial1 = &hscif1;
eth0 = &rswitch;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
/* The last 512MB is reserved for CR. */
reg = <0x0 0x48000000 0x0 0x58000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
vcc_sdhi: regulator-vcc-sdhi {
compatible = "regulator-fixed";
regulator-name = "SDHI Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&eth_serdes {
status = "okay";
};
&extal_clk {
clock-frequency = <20000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&i2c5 {
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "st,24c16", "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
};
};
&mmc0 {
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi>;
cd-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data", "hscif1_ctrl";
function = "hscif1";
};
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
sd_pins: sd {
groups = "mmc_data4", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
tsn0_pins: tsn0 {
groups = "tsn0_mdio_b", "tsn0_link_b";
function = "tsn0";
drive-strength = <18>;
power-source = <3300>;
};
tsn1_pins: tsn1 {
groups = "tsn1_mdio_b", "tsn1_link_b";
function = "tsn1";
drive-strength = <18>;
power-source = <3300>;
};
};
&rswitch {
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>;
pinctrl-names = "default";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-handle = <&ic99>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic99: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@1 {
reg = <1>;
phy-handle = <&ic102>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic102: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupt-parent = <&gpio3>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@2 {
status = "disabled";
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};
&ufs {
status = "okay";
};
&ufs30_clk {
clock-frequency = <38400000>;
};