mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe 

Use the new phy-mux clock implementation for the PCIe pipe clock muxes
so that the pipe clock source is set to the QMP PHY PLL when the
downstream pipe clock is enabled and restored to the always-on XO when
it is again disabled.

This is needed to prevent the corresponding GDSC from hanging when
enabling or disabling the PCIe power domain, something which requires a
ticking source.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220628085707.16214-1-johan+linaro@kernel.org
This commit is contained in:
Johan Hovold 2022-06-28 10:57:07 +02:00 committed by Bjorn Andersson
parent d62cac46b0
commit 9410fb9401
1 changed files with 31 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

121
drivers/clk/qcom/gcc-sc8280xp.c
View File

@ -20,6 +20,7 @@
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
@ -82,11 +83,6 @@ enum {
P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
P_PCIE_2A_PIPE_CLK,
P_PCIE_2B_PIPE_CLK,
P_PCIE_3A_PIPE_CLK,
P_PCIE_3B_PIPE_CLK,
P_PCIE_4_PIPE_CLK,
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
P_QUSB4PHY_GCC_USB4_RX0_CLK,
@ -351,56 +347,6 @@ static const struct clk_parent_data gcc_parent_data_9[] = {
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_PCIE_2A_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_PCIE_2A_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_PCIE_2B_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_PCIE_2B_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_PCIE_3A_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_PCIE_3A_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_PCIE_3B_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .index = DT_PCIE_3B_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_PCIE_4_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .index = DT_PCIE_4_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@ -741,77 +687,72 @@ static const struct clk_parent_data gcc_parent_data_41[] = {
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
};
static struct clk_regmap_mux gcc_pcie_2a_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {
.reg = 0x9d05c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_pipe_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_2A_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_2b_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {
.reg = 0x9e05c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_pipe_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_2B_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_3a_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
.reg = 0xa005c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_pipe_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_3A_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_3b_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
.reg = 0xa205c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_13,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_pipe_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_3B_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_4_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
.reg = 0x6b05c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_14,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_4_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};