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net/mlx5: DR, Add check for unsupported fields in match param
When a matcher is being built, we "consume" (clear) mask fields one by one, and to verify that we do support all the required fields we check if the whole mask was consumed, else the matching request includes unsupported fields. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
This commit is contained in:
Muhammad Sammar
Saeed Mahameed
parent
504e157248
commit
941f19798a
4 changed files with 166 additions and 127 deletions
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@ -875,9 +875,10 @@ static int dr_matcher_init_fdb(struct mlx5dr_matcher *matcher)
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static int dr_matcher_init(struct mlx5dr_matcher *matcher,
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struct mlx5dr_match_parameters *mask)
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{
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struct mlx5dr_match_parameters consumed_mask;
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struct mlx5dr_table *tbl = matcher->tbl;
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struct mlx5dr_domain *dmn = tbl->dmn;
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int ret;
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int i, ret;
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if (matcher->match_criteria >= DR_MATCHER_CRITERIA_MAX) {
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mlx5dr_err(dmn, "Invalid match criteria attribute\n");
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@ -889,8 +890,16 @@ static int dr_matcher_init(struct mlx5dr_matcher *matcher,
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mlx5dr_err(dmn, "Invalid match size attribute\n");
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return -EINVAL;
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}
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consumed_mask.match_buf = kzalloc(mask->match_sz, GFP_KERNEL);
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if (!consumed_mask.match_buf)
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return -ENOMEM;
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consumed_mask.match_sz = mask->match_sz;
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memcpy(consumed_mask.match_buf, mask->match_buf, mask->match_sz);
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mlx5dr_ste_copy_param(matcher->match_criteria,
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&matcher->mask, mask);
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&matcher->mask, &consumed_mask,
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true);
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}
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switch (dmn->type) {
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@ -909,9 +918,22 @@ static int dr_matcher_init(struct mlx5dr_matcher *matcher,
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break;
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default:
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WARN_ON(true);
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return -EINVAL;
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ret = -EINVAL;
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goto free_consumed_mask;
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}
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/* Check that all mask data was consumed */
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for (i = 0; i < consumed_mask.match_sz; i++) {
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if (consumed_mask.match_buf[i]) {
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mlx5dr_dbg(dmn, "Match param mask contains unsupported parameters\n");
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ret = -EOPNOTSUPP;
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goto free_consumed_mask;
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}
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}
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ret = 0;
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free_consumed_mask:
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kfree(consumed_mask.match_buf);
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return ret;
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}
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@ -917,7 +917,7 @@ static bool dr_rule_verify(struct mlx5dr_matcher *matcher,
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return false;
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}
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mlx5dr_ste_copy_param(matcher->match_criteria, param, value);
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mlx5dr_ste_copy_param(matcher->match_criteria, param, value, false);
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if (match_criteria & DR_MATCHER_CRITERIA_OUTER) {
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s_idx = offsetof(struct mlx5dr_match_param, outer);
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@ -668,101 +668,116 @@ int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher,
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return 0;
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}
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static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec)
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#define IFC_GET_CLR(typ, p, fld, clear) ({ \
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void *__p = (p); \
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u32 __t = MLX5_GET(typ, __p, fld); \
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if (clear) \
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MLX5_SET(typ, __p, fld, 0); \
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__t; \
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})
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#define memcpy_and_clear(to, from, len, clear) ({ \
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void *__to = (to), *__from = (from); \
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size_t __len = (len); \
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memcpy(__to, __from, __len); \
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if (clear) \
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memset(__from, 0, __len); \
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})
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static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr)
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{
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spec->gre_c_present = MLX5_GET(fte_match_set_misc, mask, gre_c_present);
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spec->gre_k_present = MLX5_GET(fte_match_set_misc, mask, gre_k_present);
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spec->gre_s_present = MLX5_GET(fte_match_set_misc, mask, gre_s_present);
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spec->source_vhca_port = MLX5_GET(fte_match_set_misc, mask, source_vhca_port);
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spec->source_sqn = MLX5_GET(fte_match_set_misc, mask, source_sqn);
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spec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr);
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spec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr);
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spec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr);
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spec->source_vhca_port = IFC_GET_CLR(fte_match_set_misc, mask, source_vhca_port, clr);
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spec->source_sqn = IFC_GET_CLR(fte_match_set_misc, mask, source_sqn, clr);
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spec->source_port = MLX5_GET(fte_match_set_misc, mask, source_port);
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spec->source_eswitch_owner_vhca_id = MLX5_GET(fte_match_set_misc, mask,
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source_eswitch_owner_vhca_id);
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spec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr);
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spec->source_eswitch_owner_vhca_id =
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IFC_GET_CLR(fte_match_set_misc, mask, source_eswitch_owner_vhca_id, clr);
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spec->outer_second_prio = MLX5_GET(fte_match_set_misc, mask, outer_second_prio);
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spec->outer_second_cfi = MLX5_GET(fte_match_set_misc, mask, outer_second_cfi);
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spec->outer_second_vid = MLX5_GET(fte_match_set_misc, mask, outer_second_vid);
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spec->inner_second_prio = MLX5_GET(fte_match_set_misc, mask, inner_second_prio);
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spec->inner_second_cfi = MLX5_GET(fte_match_set_misc, mask, inner_second_cfi);
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spec->inner_second_vid = MLX5_GET(fte_match_set_misc, mask, inner_second_vid);
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spec->outer_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_prio, clr);
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spec->outer_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cfi, clr);
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spec->outer_second_vid = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_vid, clr);
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spec->inner_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, inner_second_prio, clr);
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spec->inner_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, inner_second_cfi, clr);
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spec->inner_second_vid = IFC_GET_CLR(fte_match_set_misc, mask, inner_second_vid, clr);
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spec->outer_second_cvlan_tag =
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MLX5_GET(fte_match_set_misc, mask, outer_second_cvlan_tag);
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IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cvlan_tag, clr);
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spec->inner_second_cvlan_tag =
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MLX5_GET(fte_match_set_misc, mask, inner_second_cvlan_tag);
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IFC_GET_CLR(fte_match_set_misc, mask, inner_second_cvlan_tag, clr);
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spec->outer_second_svlan_tag =
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MLX5_GET(fte_match_set_misc, mask, outer_second_svlan_tag);
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IFC_GET_CLR(fte_match_set_misc, mask, outer_second_svlan_tag, clr);
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spec->inner_second_svlan_tag =
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MLX5_GET(fte_match_set_misc, mask, inner_second_svlan_tag);
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IFC_GET_CLR(fte_match_set_misc, mask, inner_second_svlan_tag, clr);
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spec->gre_protocol = IFC_GET_CLR(fte_match_set_misc, mask, gre_protocol, clr);
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spec->gre_protocol = MLX5_GET(fte_match_set_misc, mask, gre_protocol);
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spec->gre_key_h = IFC_GET_CLR(fte_match_set_misc, mask, gre_key.nvgre.hi, clr);
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spec->gre_key_l = IFC_GET_CLR(fte_match_set_misc, mask, gre_key.nvgre.lo, clr);
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spec->gre_key_h = MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.hi);
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spec->gre_key_l = MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.lo);
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spec->vxlan_vni = IFC_GET_CLR(fte_match_set_misc, mask, vxlan_vni, clr);
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spec->vxlan_vni = MLX5_GET(fte_match_set_misc, mask, vxlan_vni);
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spec->geneve_vni = MLX5_GET(fte_match_set_misc, mask, geneve_vni);
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spec->geneve_oam = MLX5_GET(fte_match_set_misc, mask, geneve_oam);
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spec->geneve_vni = IFC_GET_CLR(fte_match_set_misc, mask, geneve_vni, clr);
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spec->geneve_oam = IFC_GET_CLR(fte_match_set_misc, mask, geneve_oam, clr);
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spec->outer_ipv6_flow_label =
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MLX5_GET(fte_match_set_misc, mask, outer_ipv6_flow_label);
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IFC_GET_CLR(fte_match_set_misc, mask, outer_ipv6_flow_label, clr);
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spec->inner_ipv6_flow_label =
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MLX5_GET(fte_match_set_misc, mask, inner_ipv6_flow_label);
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IFC_GET_CLR(fte_match_set_misc, mask, inner_ipv6_flow_label, clr);
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spec->geneve_opt_len = MLX5_GET(fte_match_set_misc, mask, geneve_opt_len);
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spec->geneve_opt_len = IFC_GET_CLR(fte_match_set_misc, mask, geneve_opt_len, clr);
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spec->geneve_protocol_type =
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MLX5_GET(fte_match_set_misc, mask, geneve_protocol_type);
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IFC_GET_CLR(fte_match_set_misc, mask, geneve_protocol_type, clr);
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spec->bth_dst_qp = MLX5_GET(fte_match_set_misc, mask, bth_dst_qp);
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spec->bth_dst_qp = IFC_GET_CLR(fte_match_set_misc, mask, bth_dst_qp, clr);
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}
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static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec)
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static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec, bool clr)
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{
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__be32 raw_ip[4];
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spec->smac_47_16 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16);
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spec->smac_47_16 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, smac_47_16, clr);
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spec->smac_15_0 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_15_0);
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spec->ethertype = MLX5_GET(fte_match_set_lyr_2_4, mask, ethertype);
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spec->smac_15_0 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, smac_15_0, clr);
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spec->ethertype = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ethertype, clr);
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spec->dmac_47_16 = MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_47_16);
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spec->dmac_47_16 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, dmac_47_16, clr);
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spec->dmac_15_0 = MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_15_0);
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spec->first_prio = MLX5_GET(fte_match_set_lyr_2_4, mask, first_prio);
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spec->first_cfi = MLX5_GET(fte_match_set_lyr_2_4, mask, first_cfi);
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spec->first_vid = MLX5_GET(fte_match_set_lyr_2_4, mask, first_vid);
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spec->dmac_15_0 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, dmac_15_0, clr);
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spec->first_prio = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_prio, clr);
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spec->first_cfi = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_cfi, clr);
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spec->first_vid = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_vid, clr);
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spec->ip_protocol = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_protocol);
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spec->ip_dscp = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_dscp);
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spec->ip_ecn = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_ecn);
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spec->cvlan_tag = MLX5_GET(fte_match_set_lyr_2_4, mask, cvlan_tag);
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spec->svlan_tag = MLX5_GET(fte_match_set_lyr_2_4, mask, svlan_tag);
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spec->frag = MLX5_GET(fte_match_set_lyr_2_4, mask, frag);
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spec->ip_version = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_version);
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spec->tcp_flags = MLX5_GET(fte_match_set_lyr_2_4, mask, tcp_flags);
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spec->tcp_sport = MLX5_GET(fte_match_set_lyr_2_4, mask, tcp_sport);
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spec->tcp_dport = MLX5_GET(fte_match_set_lyr_2_4, mask, tcp_dport);
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spec->ip_protocol = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_protocol, clr);
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spec->ip_dscp = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_dscp, clr);
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spec->ip_ecn = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_ecn, clr);
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spec->cvlan_tag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, cvlan_tag, clr);
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spec->svlan_tag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, svlan_tag, clr);
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spec->frag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, frag, clr);
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spec->ip_version = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_version, clr);
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spec->tcp_flags = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, tcp_flags, clr);
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spec->tcp_sport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, tcp_sport, clr);
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spec->tcp_dport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, tcp_dport, clr);
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spec->ttl_hoplimit = MLX5_GET(fte_match_set_lyr_2_4, mask, ttl_hoplimit);
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spec->ttl_hoplimit = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ttl_hoplimit, clr);
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spec->udp_sport = MLX5_GET(fte_match_set_lyr_2_4, mask, udp_sport);
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spec->udp_dport = MLX5_GET(fte_match_set_lyr_2_4, mask, udp_dport);
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spec->udp_sport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, udp_sport, clr);
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spec->udp_dport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, udp_dport, clr);
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memcpy(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,
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src_ipv4_src_ipv6.ipv6_layout.ipv6),
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sizeof(raw_ip));
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memcpy_and_clear(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,
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src_ipv4_src_ipv6.ipv6_layout.ipv6),
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sizeof(raw_ip), clr);
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spec->src_ip_127_96 = be32_to_cpu(raw_ip[0]);
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spec->src_ip_95_64 = be32_to_cpu(raw_ip[1]);
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spec->src_ip_63_32 = be32_to_cpu(raw_ip[2]);
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spec->src_ip_31_0 = be32_to_cpu(raw_ip[3]);
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memcpy(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,
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dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
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sizeof(raw_ip));
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memcpy_and_clear(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,
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dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
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sizeof(raw_ip), clr);
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spec->dst_ip_127_96 = be32_to_cpu(raw_ip[0]);
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spec->dst_ip_95_64 = be32_to_cpu(raw_ip[1]);
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@ -770,104 +785,105 @@ static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec)
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spec->dst_ip_31_0 = be32_to_cpu(raw_ip[3]);
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}
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static void dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec)
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static void dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec, bool clr)
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{
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spec->outer_first_mpls_label =
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MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_label);
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IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls.mpls_label, clr);
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spec->outer_first_mpls_exp =
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MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_exp);
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IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls.mpls_exp, clr);
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spec->outer_first_mpls_s_bos =
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MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_s_bos);
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IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls.mpls_s_bos, clr);
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spec->outer_first_mpls_ttl =
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MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_ttl);
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IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls.mpls_ttl, clr);
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spec->inner_first_mpls_label =
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MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_label);
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IFC_GET_CLR(fte_match_set_misc2, mask, inner_first_mpls.mpls_label, clr);
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spec->inner_first_mpls_exp =
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MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_exp);
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IFC_GET_CLR(fte_match_set_misc2, mask, inner_first_mpls.mpls_exp, clr);
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spec->inner_first_mpls_s_bos =
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MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_s_bos);
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IFC_GET_CLR(fte_match_set_misc2, mask, inner_first_mpls.mpls_s_bos, clr);
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spec->inner_first_mpls_ttl =
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MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_ttl);
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IFC_GET_CLR(fte_match_set_misc2, mask, inner_first_mpls.mpls_ttl, clr);
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spec->outer_first_mpls_over_gre_label =
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MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_label);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_label, clr);
|
||||
spec->outer_first_mpls_over_gre_exp =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_exp);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_exp, clr);
|
||||
spec->outer_first_mpls_over_gre_s_bos =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_s_bos);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_s_bos, clr);
|
||||
spec->outer_first_mpls_over_gre_ttl =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_ttl);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_ttl, clr);
|
||||
spec->outer_first_mpls_over_udp_label =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_label);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_label, clr);
|
||||
spec->outer_first_mpls_over_udp_exp =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_exp);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_exp, clr);
|
||||
spec->outer_first_mpls_over_udp_s_bos =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_s_bos);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_s_bos, clr);
|
||||
spec->outer_first_mpls_over_udp_ttl =
|
||||
MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_ttl);
|
||||
spec->metadata_reg_c_7 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_7);
|
||||
spec->metadata_reg_c_6 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_6);
|
||||
spec->metadata_reg_c_5 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_5);
|
||||
spec->metadata_reg_c_4 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_4);
|
||||
spec->metadata_reg_c_3 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_3);
|
||||
spec->metadata_reg_c_2 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_2);
|
||||
spec->metadata_reg_c_1 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_1);
|
||||
spec->metadata_reg_c_0 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_0);
|
||||
spec->metadata_reg_a = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_a);
|
||||
IFC_GET_CLR(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_ttl, clr);
|
||||
spec->metadata_reg_c_7 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_7, clr);
|
||||
spec->metadata_reg_c_6 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_6, clr);
|
||||
spec->metadata_reg_c_5 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_5, clr);
|
||||
spec->metadata_reg_c_4 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_4, clr);
|
||||
spec->metadata_reg_c_3 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_3, clr);
|
||||
spec->metadata_reg_c_2 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_2, clr);
|
||||
spec->metadata_reg_c_1 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_1, clr);
|
||||
spec->metadata_reg_c_0 = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_c_0, clr);
|
||||
spec->metadata_reg_a = IFC_GET_CLR(fte_match_set_misc2, mask, metadata_reg_a, clr);
|
||||
}
|
||||
|
||||
static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec)
|
||||
static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec, bool clr)
|
||||
{
|
||||
spec->inner_tcp_seq_num = MLX5_GET(fte_match_set_misc3, mask, inner_tcp_seq_num);
|
||||
spec->outer_tcp_seq_num = MLX5_GET(fte_match_set_misc3, mask, outer_tcp_seq_num);
|
||||
spec->inner_tcp_ack_num = MLX5_GET(fte_match_set_misc3, mask, inner_tcp_ack_num);
|
||||
spec->outer_tcp_ack_num = MLX5_GET(fte_match_set_misc3, mask, outer_tcp_ack_num);
|
||||
spec->inner_tcp_seq_num = IFC_GET_CLR(fte_match_set_misc3, mask, inner_tcp_seq_num, clr);
|
||||
spec->outer_tcp_seq_num = IFC_GET_CLR(fte_match_set_misc3, mask, outer_tcp_seq_num, clr);
|
||||
spec->inner_tcp_ack_num = IFC_GET_CLR(fte_match_set_misc3, mask, inner_tcp_ack_num, clr);
|
||||
spec->outer_tcp_ack_num = IFC_GET_CLR(fte_match_set_misc3, mask, outer_tcp_ack_num, clr);
|
||||
spec->outer_vxlan_gpe_vni =
|
||||
MLX5_GET(fte_match_set_misc3, mask, outer_vxlan_gpe_vni);
|
||||
IFC_GET_CLR(fte_match_set_misc3, mask, outer_vxlan_gpe_vni, clr);
|
||||
spec->outer_vxlan_gpe_next_protocol =
|
||||
MLX5_GET(fte_match_set_misc3, mask, outer_vxlan_gpe_next_protocol);
|
||||
IFC_GET_CLR(fte_match_set_misc3, mask, outer_vxlan_gpe_next_protocol, clr);
|
||||
spec->outer_vxlan_gpe_flags =
|
||||
MLX5_GET(fte_match_set_misc3, mask, outer_vxlan_gpe_flags);
|
||||
spec->icmpv4_header_data = MLX5_GET(fte_match_set_misc3, mask, icmp_header_data);
|
||||
IFC_GET_CLR(fte_match_set_misc3, mask, outer_vxlan_gpe_flags, clr);
|
||||
spec->icmpv4_header_data = IFC_GET_CLR(fte_match_set_misc3, mask, icmp_header_data, clr);
|
||||
spec->icmpv6_header_data =
|
||||
MLX5_GET(fte_match_set_misc3, mask, icmpv6_header_data);
|
||||
spec->icmpv4_type = MLX5_GET(fte_match_set_misc3, mask, icmp_type);
|
||||
spec->icmpv4_code = MLX5_GET(fte_match_set_misc3, mask, icmp_code);
|
||||
spec->icmpv6_type = MLX5_GET(fte_match_set_misc3, mask, icmpv6_type);
|
||||
spec->icmpv6_code = MLX5_GET(fte_match_set_misc3, mask, icmpv6_code);
|
||||
IFC_GET_CLR(fte_match_set_misc3, mask, icmpv6_header_data, clr);
|
||||
spec->icmpv4_type = IFC_GET_CLR(fte_match_set_misc3, mask, icmp_type, clr);
|
||||
spec->icmpv4_code = IFC_GET_CLR(fte_match_set_misc3, mask, icmp_code, clr);
|
||||
spec->icmpv6_type = IFC_GET_CLR(fte_match_set_misc3, mask, icmpv6_type, clr);
|
||||
spec->icmpv6_code = IFC_GET_CLR(fte_match_set_misc3, mask, icmpv6_code, clr);
|
||||
spec->geneve_tlv_option_0_data =
|
||||
MLX5_GET(fte_match_set_misc3, mask, geneve_tlv_option_0_data);
|
||||
spec->gtpu_msg_flags = MLX5_GET(fte_match_set_misc3, mask, gtpu_msg_flags);
|
||||
spec->gtpu_msg_type = MLX5_GET(fte_match_set_misc3, mask, gtpu_msg_type);
|
||||
spec->gtpu_teid = MLX5_GET(fte_match_set_misc3, mask, gtpu_teid);
|
||||
spec->gtpu_dw_0 = MLX5_GET(fte_match_set_misc3, mask, gtpu_dw_0);
|
||||
spec->gtpu_dw_2 = MLX5_GET(fte_match_set_misc3, mask, gtpu_dw_2);
|
||||
IFC_GET_CLR(fte_match_set_misc3, mask, geneve_tlv_option_0_data, clr);
|
||||
spec->gtpu_teid = IFC_GET_CLR(fte_match_set_misc3, mask, gtpu_teid, clr);
|
||||
spec->gtpu_msg_flags = IFC_GET_CLR(fte_match_set_misc3, mask, gtpu_msg_flags, clr);
|
||||
spec->gtpu_msg_type = IFC_GET_CLR(fte_match_set_misc3, mask, gtpu_msg_type, clr);
|
||||
spec->gtpu_dw_0 = IFC_GET_CLR(fte_match_set_misc3, mask, gtpu_dw_0, clr);
|
||||
spec->gtpu_dw_2 = IFC_GET_CLR(fte_match_set_misc3, mask, gtpu_dw_2, clr);
|
||||
spec->gtpu_first_ext_dw_0 =
|
||||
MLX5_GET(fte_match_set_misc3, mask, gtpu_first_ext_dw_0);
|
||||
IFC_GET_CLR(fte_match_set_misc3, mask, gtpu_first_ext_dw_0, clr);
|
||||
}
|
||||
|
||||
static void dr_ste_copy_mask_misc4(char *mask, struct mlx5dr_match_misc4 *spec)
|
||||
static void dr_ste_copy_mask_misc4(char *mask, struct mlx5dr_match_misc4 *spec, bool clr)
|
||||
{
|
||||
spec->prog_sample_field_id_0 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_id_0);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_id_0, clr);
|
||||
spec->prog_sample_field_value_0 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_value_0);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_value_0, clr);
|
||||
spec->prog_sample_field_id_1 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_id_1);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_id_1, clr);
|
||||
spec->prog_sample_field_value_1 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_value_1);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_value_1, clr);
|
||||
spec->prog_sample_field_id_2 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_id_2);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_id_2, clr);
|
||||
spec->prog_sample_field_value_2 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_value_2);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_value_2, clr);
|
||||
spec->prog_sample_field_id_3 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_id_3);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_id_3, clr);
|
||||
spec->prog_sample_field_value_3 =
|
||||
MLX5_GET(fte_match_set_misc4, mask, prog_sample_field_value_3);
|
||||
IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_value_3, clr);
|
||||
}
|
||||
|
||||
void mlx5dr_ste_copy_param(u8 match_criteria,
|
||||
struct mlx5dr_match_param *set_param,
|
||||
struct mlx5dr_match_parameters *mask)
|
||||
struct mlx5dr_match_parameters *mask,
|
||||
bool clr)
|
||||
{
|
||||
u8 tail_param[MLX5_ST_SZ_BYTES(fte_match_set_lyr_2_4)] = {};
|
||||
u8 *data = (u8 *)mask->match_buf;
|
||||
|
|
@ -881,7 +897,7 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
|
|||
} else {
|
||||
buff = mask->match_buf;
|
||||
}
|
||||
dr_ste_copy_mask_spec(buff, &set_param->outer);
|
||||
dr_ste_copy_mask_spec(buff, &set_param->outer, clr);
|
||||
}
|
||||
param_location = sizeof(struct mlx5dr_match_spec);
|
||||
|
||||
|
|
@ -894,7 +910,7 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
|
|||
} else {
|
||||
buff = data + param_location;
|
||||
}
|
||||
dr_ste_copy_mask_misc(buff, &set_param->misc);
|
||||
dr_ste_copy_mask_misc(buff, &set_param->misc, clr);
|
||||
}
|
||||
param_location += sizeof(struct mlx5dr_match_misc);
|
||||
|
||||
|
|
@ -907,7 +923,7 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
|
|||
} else {
|
||||
buff = data + param_location;
|
||||
}
|
||||
dr_ste_copy_mask_spec(buff, &set_param->inner);
|
||||
dr_ste_copy_mask_spec(buff, &set_param->inner, clr);
|
||||
}
|
||||
param_location += sizeof(struct mlx5dr_match_spec);
|
||||
|
||||
|
|
@ -920,7 +936,7 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
|
|||
} else {
|
||||
buff = data + param_location;
|
||||
}
|
||||
dr_ste_copy_mask_misc2(buff, &set_param->misc2);
|
||||
dr_ste_copy_mask_misc2(buff, &set_param->misc2, clr);
|
||||
}
|
||||
|
||||
param_location += sizeof(struct mlx5dr_match_misc2);
|
||||
|
|
@ -934,7 +950,7 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
|
|||
} else {
|
||||
buff = data + param_location;
|
||||
}
|
||||
dr_ste_copy_mask_misc3(buff, &set_param->misc3);
|
||||
dr_ste_copy_mask_misc3(buff, &set_param->misc3, clr);
|
||||
}
|
||||
|
||||
param_location += sizeof(struct mlx5dr_match_misc3);
|
||||
|
|
@ -948,7 +964,7 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
|
|||
} else {
|
||||
buff = data + param_location;
|
||||
}
|
||||
dr_ste_copy_mask_misc4(buff, &set_param->misc4);
|
||||
dr_ste_copy_mask_misc4(buff, &set_param->misc4, clr);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1230,7 +1230,8 @@ void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx,
|
|||
struct mlx5dr_htbl_connect_info *connect_info);
|
||||
void mlx5dr_ste_copy_param(u8 match_criteria,
|
||||
struct mlx5dr_match_param *set_param,
|
||||
struct mlx5dr_match_parameters *mask);
|
||||
struct mlx5dr_match_parameters *mask,
|
||||
bool clear);
|
||||
|
||||
struct mlx5dr_qp {
|
||||
struct mlx5_core_dev *mdev;
|
||||
|
|
|
|||
Loading…
Reference in a new issue