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drm/i915: Introduce Jasper Lake PCH
The Jasper Lake PCH follows ICP/TGP's south display behavior and is identical to MCC graphics-wise except that it does not use the unusual (port C -> TC1) pin mapping that MCC does. Also, it turns out the extra PCH ID that we had previously thought was a form of MCC is actually a second ID for JSP (i.e., port C uses the port C pins instead of the TC1 pins). v2: - Also update the port masks (not just the pin table) in mcc_hpd_irq_setup. (Vivek) v3: - Break jsp_hpd_irq_setup out into its own function for clarity. (Vivek) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191015162854.30546-1-matthew.d.roper@intel.com
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3 changed files with 32 additions and 3 deletions
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@ -2248,12 +2248,19 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
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tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
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pins = hpd_tgp;
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} else if (HAS_PCH_JSP(dev_priv)) {
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ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
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tc_hotplug_trigger = 0;
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pins = hpd_tgp;
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} else if (HAS_PCH_MCC(dev_priv)) {
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ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
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tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
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tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
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pins = hpd_icp;
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} else {
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WARN(!HAS_PCH_ICP(dev_priv),
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"Unrecognized PCH type 0x%x\n", INTEL_PCH_TYPE(dev_priv));
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ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
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tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
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tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
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@ -3383,6 +3390,19 @@ static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
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hpd_icp);
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}
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/*
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* JSP behaves exactly the same as MCC above except that port C is mapped to
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* the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
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* masks & tables rather than ICP's masks & tables.
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*/
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static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
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{
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icp_hpd_irq_setup(dev_priv,
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SDE_DDI_MASK_TGP, 0,
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TGP_DDI_HPD_ENABLE_MASK, 0,
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hpd_tgp);
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}
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static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
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{
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u32 hotplug;
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@ -4314,7 +4334,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
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if (I915_HAS_HOTPLUG(dev_priv))
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dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
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} else {
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if (HAS_PCH_MCC(dev_priv))
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if (HAS_PCH_JSP(dev_priv))
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dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
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else if (HAS_PCH_MCC(dev_priv))
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dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
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else if (INTEL_GEN(dev_priv) >= 11)
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dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
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@ -79,7 +79,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
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WARN_ON(!IS_ICELAKE(dev_priv));
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return PCH_ICP;
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case INTEL_PCH_MCC_DEVICE_ID_TYPE:
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case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
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DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
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WARN_ON(!IS_ELKHARTLAKE(dev_priv));
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return PCH_MCC;
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@ -87,6 +86,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
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DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
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WARN_ON(!IS_TIGERLAKE(dev_priv));
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return PCH_TGP;
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case INTEL_PCH_JSP_DEVICE_ID_TYPE:
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case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
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DRM_DEBUG_KMS("Found Jasper Lake PCH\n");
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WARN_ON(!IS_ELKHARTLAKE(dev_priv));
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return PCH_JSP;
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default:
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return PCH_NONE;
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}
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@ -23,6 +23,7 @@ enum intel_pch {
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PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
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PCH_CNP, /* Cannon/Comet Lake PCH */
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PCH_ICP, /* Ice Lake PCH */
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PCH_JSP, /* Jasper Lake PCH */
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PCH_MCC, /* Mule Creek Canyon PCH */
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PCH_TGP, /* Tiger Lake PCH */
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};
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@ -44,14 +45,16 @@ enum intel_pch {
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#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
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#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
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#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
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#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
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#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
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#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
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#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
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#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
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#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
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#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
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#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
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#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
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#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
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