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[MIPS] Make SB1 cache flushes not to use on_each_cpu
This fixes the start_kernel(): bug: interrupts were enabled early messages. Signed-off-by: Manish Lachwani <mlachwani@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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parent
f0ec69e529
commit
9448b8f6a0
1 changed files with 13 additions and 4 deletions
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@ -49,6 +49,15 @@ static unsigned short dcache_sets;
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static unsigned int icache_range_cutoff;
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static unsigned int dcache_range_cutoff;
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static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
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int retry, int wait)
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{
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preempt_disable();
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smp_call_function(func, info, retry, wait);
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func(info);
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preempt_enable();
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}
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/*
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* The dcache is fully coherent to the system, with one
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* big caveat: the instruction stream. In other words,
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@ -226,7 +235,7 @@ static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
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args.vma = vma;
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args.addr = addr;
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args.pfn = pfn;
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on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
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sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
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}
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#else
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void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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@ -249,7 +258,7 @@ void sb1___flush_cache_all_ipi(void *ignored)
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static void sb1___flush_cache_all(void)
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{
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on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
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sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
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}
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#else
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void sb1___flush_cache_all(void)
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@ -299,7 +308,7 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end)
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args.start = start;
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args.end = end;
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on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
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sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
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}
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#else
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void sb1_flush_icache_range(unsigned long start, unsigned long end)
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@ -326,7 +335,7 @@ static void sb1_flush_cache_sigtramp_ipi(void *info)
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static void sb1_flush_cache_sigtramp(unsigned long addr)
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{
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on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
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sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
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}
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#else
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void sb1_flush_cache_sigtramp(unsigned long addr)
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