gpio: intel-mid: Remove driver for deprecated platform
Intel Moorestown and Medfield are quite old Intel Atom based
32-bit platforms, which were in limited use in some Android phones,
tablets and consumer electronics more than eight years ago.
There are no bugs or problems ever reported outside from Intel
for breaking any of that platforms for years. It seems no real
users exists who run more or less fresh kernel on it. The commit
05f4434bc1 ("ASoC: Intel: remove mfld_machine") also in align
with this theory.
Due to above and to reduce a burden of supporting outdated drivers
we remove the support of outdated platforms completely.
Moreover this code duplicates gpio-pxa since the IP has been derived
from XScale implementation. If anybody wants to resurrect this
it has to be part of gpio-pxa.c.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andy Shevchenko
Bartosz Golaszewski
parent
fe08e9e26a
commit
944dcbe84b
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@ -8936,7 +8936,6 @@ L: linux-gpio@vger.kernel.org
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
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F: drivers/gpio/gpio-ich.c
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F: drivers/gpio/gpio-intel-mid.c
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F: drivers/gpio/gpio-merrifield.c
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F: drivers/gpio/gpio-ml-ioh.c
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F: drivers/gpio/gpio-pch.c
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@ -1451,13 +1451,6 @@ config GPIO_BT8XX
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If unsure, say N.
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config GPIO_INTEL_MID
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bool "Intel MID GPIO support"
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depends on X86_INTEL_MID
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select GPIOLIB_IRQCHIP
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help
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Say Y here to support Intel MID GPIO.
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config GPIO_MERRIFIELD
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tristate "Intel Merrifield GPIO support"
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depends on X86_INTEL_MID
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@ -67,7 +67,6 @@ obj-$(CONFIG_GPIO_HISI) += gpio-hisi.o
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obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o
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obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
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obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
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obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o
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obj-$(CONFIG_GPIO_IOP) += gpio-iop.o
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obj-$(CONFIG_GPIO_IT87) += gpio-it87.o
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obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o
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@ -101,7 +101,7 @@ for a few GPIOs. Those should stay where they are.
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At the same time it makes sense to get rid of code duplication in existing or
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new coming drivers. For example, gpio-ml-ioh should be incorporated into
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gpio-pch. In similar way gpio-intel-mid into gpio-pxa.
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gpio-pch.
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Generic MMIO GPIO
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@ -1,414 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel MID GPIO driver
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*
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* Copyright (c) 2008-2014,2016 Intel Corporation.
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*/
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/* Supports:
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* Moorestown platform Langwell chip.
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* Medfield platform Penwell chip.
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* Clovertrail platform Cloverview chip.
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*/
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#include <linux/delay.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
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#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
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* registers to control them, so we only define the order here instead of a
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* structure, to get a bit offset for a pin (use GPDR as an example):
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*
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* nreg = ngpio / 32;
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* reg = offset / 32;
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* bit = offset % 32;
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* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
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*
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* so the bit of reg_addr is to control pin offset's GPDR feature
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*/
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enum GPIO_REG {
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GPLR = 0, /* pin level read-only */
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GPDR, /* pin direction */
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GPSR, /* pin set */
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GPCR, /* pin clear */
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GRER, /* rising edge detect */
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GFER, /* falling edge detect */
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GEDR, /* edge detect result */
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GAFR, /* alt function */
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};
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/* intel_mid gpio driver data */
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struct intel_mid_gpio_ddata {
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u16 ngpio; /* number of gpio pins */
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u32 chip_irq_type; /* chip interrupt type */
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};
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struct intel_mid_gpio {
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struct gpio_chip chip;
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void __iomem *reg_base;
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spinlock_t lock;
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struct pci_dev *pdev;
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};
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct intel_mid_gpio *priv = gpiochip_get_data(chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 32;
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return priv->reg_base + reg_type * nreg * 4 + reg * 4;
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}
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static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct intel_mid_gpio *priv = gpiochip_get_data(chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 16;
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return priv->reg_base + reg_type * nreg * 4 + reg * 4;
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}
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static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
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u32 value = readl(gafr);
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int shift = (offset % 16) << 1, af = (value >> shift) & 3;
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if (af) {
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value &= ~(3 << shift);
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writel(value, gafr);
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}
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return 0;
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}
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static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gplr = gpio_reg(chip, offset, GPLR);
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return !!(readl(gplr) & BIT(offset % 32));
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}
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static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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void __iomem *gpsr, *gpcr;
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if (value) {
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gpsr = gpio_reg(chip, offset, GPSR);
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writel(BIT(offset % 32), gpsr);
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} else {
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gpcr = gpio_reg(chip, offset, GPCR);
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writel(BIT(offset % 32), gpcr);
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}
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}
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static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct intel_mid_gpio *priv = gpiochip_get_data(chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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u32 value;
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unsigned long flags;
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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spin_lock_irqsave(&priv->lock, flags);
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value = readl(gpdr);
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value &= ~BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&priv->lock, flags);
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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return 0;
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}
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static int intel_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct intel_mid_gpio *priv = gpiochip_get_data(chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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unsigned long flags;
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intel_gpio_set(chip, offset, value);
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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spin_lock_irqsave(&priv->lock, flags);
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value = readl(gpdr);
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value |= BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&priv->lock, flags);
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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return 0;
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}
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static int intel_mid_irq_type(struct irq_data *d, unsigned type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_mid_gpio *priv = gpiochip_get_data(gc);
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u32 gpio = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
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void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
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if (gpio >= priv->chip.ngpio)
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return -EINVAL;
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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spin_lock_irqsave(&priv->lock, flags);
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if (type & IRQ_TYPE_EDGE_RISING)
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value = readl(grer) | BIT(gpio % 32);
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else
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value = readl(grer) & (~BIT(gpio % 32));
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writel(value, grer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = readl(gfer) | BIT(gpio % 32);
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else
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value = readl(gfer) & (~BIT(gpio % 32));
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writel(value, gfer);
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spin_unlock_irqrestore(&priv->lock, flags);
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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return 0;
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}
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static void intel_mid_irq_unmask(struct irq_data *d)
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{
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}
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static void intel_mid_irq_mask(struct irq_data *d)
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{
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}
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static struct irq_chip intel_mid_irqchip = {
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.name = "INTEL_MID-GPIO",
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.irq_mask = intel_mid_irq_mask,
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.irq_unmask = intel_mid_irq_unmask,
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.irq_set_type = intel_mid_irq_type,
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};
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static const struct intel_mid_gpio_ddata gpio_lincroft = {
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.ngpio = 64,
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};
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static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct intel_mid_gpio_ddata gpio_penwell_core = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
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};
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static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct pci_device_id intel_gpio_ids[] = {
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{
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/* Lincroft */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
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.driver_data = (kernel_ulong_t)&gpio_lincroft,
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},
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{
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/* Penwell AON */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
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.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
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},
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{
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/* Penwell Core */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
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.driver_data = (kernel_ulong_t)&gpio_penwell_core,
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},
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{
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/* Cloverview Aon */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
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.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
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},
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{
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/* Cloverview Core */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
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.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
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},
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{ }
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};
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static void intel_mid_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct intel_mid_gpio *priv = gpiochip_get_data(gc);
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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u32 base, gpio, mask;
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unsigned long pending;
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void __iomem *gedr;
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/* check GPIO controller to check which pin triggered the interrupt */
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for (base = 0; base < priv->chip.ngpio; base += 32) {
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gedr = gpio_reg(&priv->chip, base, GEDR);
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while ((pending = readl(gedr))) {
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gpio = __ffs(pending);
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mask = BIT(gpio);
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/* Clear before handling so we can't lose an edge */
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writel(mask, gedr);
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generic_handle_irq(irq_find_mapping(gc->irq.domain,
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base + gpio));
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}
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}
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chip->irq_eoi(data);
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}
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static int intel_mid_irq_init_hw(struct gpio_chip *chip)
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{
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struct intel_mid_gpio *priv = gpiochip_get_data(chip);
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void __iomem *reg;
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unsigned base;
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for (base = 0; base < priv->chip.ngpio; base += 32) {
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/* Clear the rising-edge detect register */
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reg = gpio_reg(&priv->chip, base, GRER);
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writel(0, reg);
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/* Clear the falling-edge detect register */
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reg = gpio_reg(&priv->chip, base, GFER);
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writel(0, reg);
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/* Clear the edge detect status register */
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reg = gpio_reg(&priv->chip, base, GEDR);
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writel(~0, reg);
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}
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return 0;
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}
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static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
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{
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int err = pm_schedule_suspend(dev, 500);
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return err ?: -EBUSY;
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}
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static const struct dev_pm_ops intel_gpio_pm_ops = {
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SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
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};
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static int intel_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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void __iomem *base;
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struct intel_mid_gpio *priv;
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u32 gpio_base;
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u32 irq_base;
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int retval;
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struct gpio_irq_chip *girq;
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struct intel_mid_gpio_ddata *ddata =
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(struct intel_mid_gpio_ddata *)id->driver_data;
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retval = pcim_enable_device(pdev);
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if (retval)
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return retval;
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retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
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if (retval) {
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dev_err(&pdev->dev, "I/O memory mapping error\n");
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return retval;
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}
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base = pcim_iomap_table(pdev)[1];
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irq_base = readl(base);
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gpio_base = readl(sizeof(u32) + base);
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/* release the IO mapping, since we already get the info from bar1 */
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pcim_iounmap_regions(pdev, 1 << 1);
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->reg_base = pcim_iomap_table(pdev)[0];
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priv->chip.label = dev_name(&pdev->dev);
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priv->chip.parent = &pdev->dev;
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priv->chip.request = intel_gpio_request;
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priv->chip.direction_input = intel_gpio_direction_input;
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priv->chip.direction_output = intel_gpio_direction_output;
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priv->chip.get = intel_gpio_get;
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priv->chip.set = intel_gpio_set;
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priv->chip.base = gpio_base;
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priv->chip.ngpio = ddata->ngpio;
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priv->chip.can_sleep = false;
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priv->pdev = pdev;
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spin_lock_init(&priv->lock);
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girq = &priv->chip.irq;
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girq->chip = &intel_mid_irqchip;
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girq->init_hw = intel_mid_irq_init_hw;
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girq->parent_handler = intel_mid_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = pdev->irq;
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girq->first = irq_base;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_simple_irq;
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pci_set_drvdata(pdev, priv);
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retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
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if (retval) {
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dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
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return retval;
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}
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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}
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static struct pci_driver intel_gpio_driver = {
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.name = "intel_mid_gpio",
|
||||
.id_table = intel_gpio_ids,
|
||||
.probe = intel_gpio_probe,
|
||||
.driver = {
|
||||
.pm = &intel_gpio_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_pci_driver(intel_gpio_driver);
|
||||
Loading…
Reference in New Issue