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[POWERPC] spufs: don't set reserved bits in spu interrupt status 

This changes the spu context switch code to not write to reserved bits
of spu interrupt status register.
The architecture book says the reserved fields should be set to zero.

Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Masato Noguchi 2007-12-20 16:39:59 +09:00 committed by Paul Mackerras
parent b192541b39
commit 9476141c18
2 changed files with 12 additions and 10 deletions
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20
arch/powerpc/platforms/cell/spufs/switch.c
View File

@ -740,9 +740,9 @@ static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
* (translation) interrupts.
*/
spin_lock_irq(&spu->register_lock);
spu_int_stat_clear(spu, 0, ~0ul);
spu_int_stat_clear(spu, 1, ~0ul);
spu_int_stat_clear(spu, 2, ~0ul);
spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
spu_int_mask_set(spu, 0, 0ul);
spu_int_mask_set(spu, 1, class1_mask);
spu_int_mask_set(spu, 2, 0ul);
@ -899,8 +899,8 @@ static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
local_irq_save(flags);
spu_int_stat_clear(spu, 0, ~(0ul));
spu_int_stat_clear(spu, 2, ~(0ul));
spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
local_irq_restore(flags);
}
@ -918,8 +918,8 @@ static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
local_irq_save(flags);
spu_int_stat_clear(spu, 0, ~(0ul));
spu_int_stat_clear(spu, 2, ~(0ul));
spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
local_irq_restore(flags);
}
@ -1395,9 +1395,9 @@ static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
spu_int_mask_set(spu, 0, 0ul);
spu_int_mask_set(spu, 1, 0ul);
spu_int_mask_set(spu, 2, 0ul);
spu_int_stat_clear(spu, 0, ~0ul);
spu_int_stat_clear(spu, 1, ~0ul);
spu_int_stat_clear(spu, 2, ~0ul);
spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
spin_unlock_irq(&spu->register_lock);
}

2
include/asm-powerpc/spu.h
View File

@ -535,11 +535,13 @@ struct spu_priv1 {
#define CLASS1_STORAGE_FAULT_INTR 0x2L
#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
#define CLASS1_INTR_MASK 0xfL
#define CLASS2_MAILBOX_INTR 0x1L
#define CLASS2_SPU_STOP_INTR 0x2L
#define CLASS2_SPU_HALT_INTR 0x4L
#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
#define CLASS2_INTR_MASK 0x1fL
u8 pad_0x158_0x180[0x28]; /* 0x158 */
u64 int_route_RW; /* 0x180 */