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drm/amd/pp: Refine pp_dpm_force_clock_level functions
Only when user set manual performance mode, driver enable pp_dpm_force_clock_level. so check the mode in pp_dpm_force_clock_level, and delete the same logic in callback functions. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6fa3ef3a9c
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948fd66c94
5 changed files with 5 additions and 17 deletions
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@ -6639,9 +6639,7 @@ static int ci_dpm_force_clock_level(void *handle,
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ci_power_info *pi = ci_get_pi(adev);
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struct ci_power_info *pi = ci_get_pi(adev);
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if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
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if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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AMD_DPM_FORCED_LEVEL_LOW |
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AMD_DPM_FORCED_LEVEL_HIGH))
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return -EINVAL;
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return -EINVAL;
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switch (type) {
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switch (type) {
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@ -839,7 +839,10 @@ static int pp_dpm_force_clock_level(void *handle,
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return 0;
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return 0;
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}
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}
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mutex_lock(&pp_handle->pp_lock);
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mutex_lock(&pp_handle->pp_lock);
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hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
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ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
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else
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ret = -EINVAL;
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mutex_unlock(&pp_handle->pp_lock);
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mutex_unlock(&pp_handle->pp_lock);
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return ret;
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return ret;
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}
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}
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@ -1558,9 +1558,6 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
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static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask)
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enum pp_clock_type type, uint32_t mask)
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{
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{
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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return -EINVAL;
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switch (type) {
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switch (type) {
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case PP_SCLK:
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case PP_SCLK:
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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@ -4296,11 +4296,6 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
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{
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
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AMD_DPM_FORCED_LEVEL_LOW |
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AMD_DPM_FORCED_LEVEL_HIGH))
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return -EINVAL;
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switch (type) {
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switch (type) {
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case PP_SCLK:
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case PP_SCLK:
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if (!data->sclk_dpm_key_disabled)
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if (!data->sclk_dpm_key_disabled)
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@ -4500,11 +4500,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
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{
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
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AMD_DPM_FORCED_LEVEL_LOW |
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AMD_DPM_FORCED_LEVEL_HIGH))
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return -EINVAL;
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switch (type) {
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switch (type) {
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case PP_SCLK:
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case PP_SCLK:
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data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
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data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
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