mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-15 23:25:07 +00:00
Devicetree updates for 3.11
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRrO92AAoJEAKiPfwuf9N/LsgH/RjLx3DuFYA3WjMgBXyX/wyt 7FKq7qbCd10jNm67+yPOEwGDKcBq6tOVGUpsv95gj9vZA4/w5qsSXiHM5chREyca T6qqUgUc6Q8raeqiLys6cyk2ivfZBW3fGd0uvj2RlnmEqWfvkuijta1tfp4aIPhv 2s2pMJcsLKeUTBx3/wtZeY2kGuY0Zs5JHGeXOSgpYwDuXYo/ymFeMQnHIgP2S+TO xDgWDX6Sou9dHKiMZ6/ZGcBXTjD8iKDrBFs+N3gApfcNS/bhiZDZ1v6zWg6OIinB tYjeDpISDto2wvCybGfEZMzNTyRc7l2mIIjlcJ/rVz3cc983P41bEXHXaeZYsqg= =iXVY -----END PGP SIGNATURE----- Merge tag 'vt8500/dts-3.11' of git://github.com/linux-wmt/linux-vtwm into next/dt From Tony Prisk, vt8500 devicetree updates for 3.11. * tag 'vt8500/dts-3.11' of git://github.com/linux-wmt/linux-vtwm: dts: vt8500: Correct reference clock on WM8850 SoCs dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files dts: vt8500: Populate missing PLL nodes dts: clk: vt8500: Update SoC dtsi to use WM8850 PLL clocks dts: vt8500: Update serial nodes and disable by default in SoC files dts: vt8500: Add devicetree support for WM8750 SoC and APC8750 board dts: vt8500: Fix invalid/missing cpu nodes for soc files. Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
94937fff01
11 changed files with 649 additions and 30 deletions
|
@ -211,6 +211,7 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
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dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
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wm8505-ref.dtb \
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wm8650-mid.dtb \
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wm8750-apc8750.dtb \
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wm8850-w70v2.dtb
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dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
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@ -30,3 +30,7 @@ timing0: 800x480 {
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -11,6 +11,23 @@
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/ {
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compatible = "via,vt8500";
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -111,32 +128,36 @@ ge_rops@d8050400 {
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reg = <0xd8050400 0x100>;
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};
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uart@d8200000 {
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uart0: serial@d8200000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8200000 0x1040>;
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interrupts = <32>;
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clocks = <&clkuart0>;
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status = "disabled";
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};
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uart@d82b0000 {
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uart1: serial@d82b0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82b0000 0x1040>;
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interrupts = <33>;
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clocks = <&clkuart1>;
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status = "disabled";
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};
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uart@d8210000 {
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uart2: serial@d8210000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8210000 0x1040>;
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interrupts = <47>;
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clocks = <&clkuart2>;
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status = "disabled";
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};
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uart@d82c0000 {
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uart3: serial@d82c0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82c0000 0x1040>;
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interrupts = <50>;
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clocks = <&clkuart3>;
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status = "disabled";
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};
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rtc@d8100000 {
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@ -30,3 +30,7 @@ timing0: 800x480 {
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -12,11 +12,24 @@ / {
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compatible = "wm,wm8505";
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -68,6 +81,13 @@ ref25: ref25M {
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clock-frequency = <25000000>;
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};
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plla: plla {
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#clock-cells = <0>;
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compatible = "via,vt8500-pll-clock";
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clocks = <&ref25>;
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reg = <0x200>;
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};
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pllb: pllb {
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#clock-cells = <0>;
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compatible = "via,vt8500-pll-clock";
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@ -75,6 +95,48 @@ pllb: pllb {
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reg = <0x204>;
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};
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pllc: pllc {
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#clock-cells = <0>;
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compatible = "via,vt8500-pll-clock";
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clocks = <&ref25>;
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reg = <0x208>;
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};
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plld: plld {
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#clock-cells = <0>;
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compatible = "via,vt8500-pll-clock";
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clocks = <&ref25>;
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reg = <0x20c>;
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};
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clkarm: arm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plla>;
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divisor-reg = <0x300>;
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};
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clkahb: ahb {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x304>;
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};
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clkapb: apb {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x350>;
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};
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clkddr: ddr {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plld>;
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divisor-reg = <0x310>;
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};
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clkuart0: uart0 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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@ -163,46 +225,52 @@ ge_rops@d8050400 {
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reg = <0xd8050400 0x100>;
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};
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uart@d8200000 {
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uart0: serial@d8200000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8200000 0x1040>;
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interrupts = <32>;
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clocks = <&clkuart0>;
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status = "disabled";
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};
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uart@d82b0000 {
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uart1: serial@d82b0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82b0000 0x1040>;
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interrupts = <33>;
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clocks = <&clkuart1>;
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status = "disabled";
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};
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uart@d8210000 {
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uart2: serial@d8210000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8210000 0x1040>;
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interrupts = <47>;
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clocks = <&clkuart2>;
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status = "disabled";
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};
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uart@d82c0000 {
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uart3: serial@d82c0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82c0000 0x1040>;
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interrupts = <50>;
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clocks = <&clkuart3>;
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status = "disabled";
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};
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uart@d8370000 {
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uart4: serial@d8370000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8370000 0x1040>;
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interrupts = <31>;
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clocks = <&clkuart4>;
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status = "disabled";
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};
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uart@d8380000 {
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uart5: serial@d8380000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8380000 0x1040>;
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interrupts = <30>;
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clocks = <&clkuart5>;
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status = "disabled";
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};
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rtc@d8100000 {
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@ -32,3 +32,6 @@ timing0: 800x480 {
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -11,6 +11,21 @@
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/ {
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compatible = "wm,wm8650";
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -77,6 +92,55 @@ pllb: pllb {
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reg = <0x204>;
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};
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pllc: pllc {
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#clock-cells = <0>;
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compatible = "wm,wm8650-pll-clock";
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clocks = <&ref25>;
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reg = <0x208>;
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};
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plld: plld {
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#clock-cells = <0>;
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compatible = "wm,wm8650-pll-clock";
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clocks = <&ref25>;
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reg = <0x20c>;
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};
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plle: plle {
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#clock-cells = <0>;
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compatible = "wm,wm8650-pll-clock";
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clocks = <&ref25>;
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reg = <0x210>;
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};
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clkarm: arm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plla>;
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divisor-reg = <0x300>;
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};
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clkahb: ahb {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x304>;
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};
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clkapb: apb {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x320>;
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};
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clkddr: ddr {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plld>;
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divisor-reg = <0x310>;
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};
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clkuart0: uart0 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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@ -93,14 +157,7 @@ clkuart1: uart1 {
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enable-bit = <2>;
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};
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arm: arm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plla>;
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divisor-reg = <0x300>;
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};
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sdhc: sdhc {
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clksdhc: sdhc {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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|
@ -140,18 +197,20 @@ ge_rops@d8050400 {
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reg = <0xd8050400 0x100>;
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};
|
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uart@d8200000 {
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uart0: serial@d8200000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8200000 0x1040>;
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interrupts = <32>;
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clocks = <&clkuart0>;
|
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status = "disabled";
|
||||
};
|
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|
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uart@d82b0000 {
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uart1: serial@d82b0000 {
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compatible = "via,vt8500-uart";
|
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reg = <0xd82b0000 0x1040>;
|
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interrupts = <33>;
|
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clocks = <&clkuart1>;
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status = "disabled";
|
||||
};
|
||||
|
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rtc@d8100000 {
|
||||
|
|
30
arch/arm/boot/dts/wm8750-apc8750.dts
Normal file
30
arch/arm/boot/dts/wm8750-apc8750.dts
Normal file
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* wm8750-apc8750.dts
|
||||
* - Device tree file for VIA APC8750
|
||||
*
|
||||
* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
|
||||
*
|
||||
* Licensed under GPLv2 or later
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "wm8750.dtsi"
|
||||
|
||||
/ {
|
||||
model = "VIA APC8750";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c>;
|
||||
|
||||
i2c: i2c {
|
||||
wm,pins = <168 169 170 171>;
|
||||
wm,function = <2>; /* alt */
|
||||
wm,pull = <2>; /* pull-up */
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
347
arch/arm/boot/dts/wm8750.dtsi
Normal file
347
arch/arm/boot/dts/wm8750.dtsi
Normal file
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
|
||||
*
|
||||
* Licensed under GPLv2 or later
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "wm,wm8750";
|
||||
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm1176ej-s";
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
i2c0 = &i2c_0;
|
||||
i2c1 = &i2c_1;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
interrupt-parent = <&intc0>;
|
||||
|
||||
intc0: interrupt-controller@d8140000 {
|
||||
compatible = "via,vt8500-intc";
|
||||
interrupt-controller;
|
||||
reg = <0xd8140000 0x10000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
/* Secondary IC cascaded to intc0 */
|
||||
intc1: interrupt-controller@d8150000 {
|
||||
compatible = "via,vt8500-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xD8150000 0x10000>;
|
||||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8750-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
compatible = "via,vt8500-pmc";
|
||||
reg = <0xd8130000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ref24: ref24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
ref25: ref25M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
plla: plla {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
reg = <0x200>;
|
||||
};
|
||||
|
||||
pllb: pllb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
reg = <0x204>;
|
||||
};
|
||||
|
||||
pllc: pllc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
reg = <0x208>;
|
||||
};
|
||||
|
||||
plld: plld {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
reg = <0x20C>;
|
||||
};
|
||||
|
||||
plle: plle {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
reg = <0x210>;
|
||||
};
|
||||
|
||||
clkarm: arm {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&plla>;
|
||||
divisor-reg = <0x300>;
|
||||
};
|
||||
|
||||
clkahb: ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x304>;
|
||||
};
|
||||
|
||||
clkapb: apb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x320>;
|
||||
};
|
||||
|
||||
clkddr: ddr {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&plld>;
|
||||
divisor-reg = <0x310>;
|
||||
};
|
||||
|
||||
clkuart0: uart0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&ref24>;
|
||||
enable-reg = <0x254>;
|
||||
enable-bit = <24>;
|
||||
};
|
||||
|
||||
clkuart1: uart1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&ref24>;
|
||||
enable-reg = <0x254>;
|
||||
enable-bit = <25>;
|
||||
};
|
||||
|
||||
clkuart2: uart2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&ref24>;
|
||||
enable-reg = <0x254>;
|
||||
enable-bit = <26>;
|
||||
};
|
||||
|
||||
clkuart3: uart3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&ref24>;
|
||||
enable-reg = <0x254>;
|
||||
enable-bit = <27>;
|
||||
};
|
||||
|
||||
clkuart4: uart4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&ref24>;
|
||||
enable-reg = <0x254>;
|
||||
enable-bit = <28>;
|
||||
};
|
||||
|
||||
clkuart5: uart5 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&ref24>;
|
||||
enable-reg = <0x254>;
|
||||
enable-bit = <29>;
|
||||
};
|
||||
|
||||
clkpwm: pwm {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x350>;
|
||||
enable-reg = <0x250>;
|
||||
enable-bit = <17>;
|
||||
};
|
||||
|
||||
clksdhc: sdhc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x330>;
|
||||
divisor-mask = <0x3f>;
|
||||
enable-reg = <0x250>;
|
||||
enable-bit = <0>;
|
||||
};
|
||||
|
||||
clki2c0: i2c0clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x3A0>;
|
||||
enable-reg = <0x250>;
|
||||
enable-bit = <8>;
|
||||
};
|
||||
|
||||
clki2c1: i2c1clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x3A4>;
|
||||
enable-reg = <0x250>;
|
||||
enable-bit = <9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm: pwm@d8220000 {
|
||||
#pwm-cells = <3>;
|
||||
compatible = "via,vt8500-pwm";
|
||||
reg = <0xd8220000 0x100>;
|
||||
clocks = <&clkpwm>;
|
||||
};
|
||||
|
||||
timer@d8130100 {
|
||||
compatible = "via,vt8500-timer";
|
||||
reg = <0xd8130100 0x28>;
|
||||
interrupts = <36>;
|
||||
};
|
||||
|
||||
ehci@d8007900 {
|
||||
compatible = "via,vt8500-ehci";
|
||||
reg = <0xd8007900 0x200>;
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
uhci@d8007b00 {
|
||||
compatible = "platform-uhci";
|
||||
reg = <0xd8007b00 0x200>;
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
uhci@d8008d00 {
|
||||
compatible = "platform-uhci";
|
||||
reg = <0xd8008d00 0x200>;
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
uart0: serial@d8200000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd8200000 0x1040>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clkuart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@d82b0000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd82b0000 0x1040>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clkuart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@d8210000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd8210000 0x1040>;
|
||||
interrupts = <47>;
|
||||
clocks = <&clkuart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@d82c0000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd82c0000 0x1040>;
|
||||
interrupts = <50>;
|
||||
clocks = <&clkuart3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@d8370000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd8370000 0x1040>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clkuart4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@d8380000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd8380000 0x1040>;
|
||||
interrupts = <43>;
|
||||
clocks = <&clkuart5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@d8100000 {
|
||||
compatible = "via,vt8500-rtc";
|
||||
reg = <0xd8100000 0x10000>;
|
||||
interrupts = <48>;
|
||||
};
|
||||
|
||||
sdhc@d800a000 {
|
||||
compatible = "wm,wm8505-sdhc";
|
||||
reg = <0xd800a000 0x1000>;
|
||||
interrupts = <20 21>;
|
||||
clocks = <&clksdhc>;
|
||||
bus-width = <4>;
|
||||
sdon-inverted;
|
||||
};
|
||||
|
||||
i2c_0: i2c@d8280000 {
|
||||
compatible = "wm,wm8505-i2c";
|
||||
reg = <0xd8280000 0x1000>;
|
||||
interrupts = <19>;
|
||||
clocks = <&clki2c0>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c_1: i2c@d8320000 {
|
||||
compatible = "wm,wm8505-i2c";
|
||||
reg = <0xd8320000 0x1000>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clki2c1>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -41,3 +41,7 @@ timing0: 800x480 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -11,6 +11,17 @@
|
|||
/ {
|
||||
compatible = "wm,wm8850";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
|
@ -72,18 +83,81 @@ ref24: ref24M {
|
|||
|
||||
plla: plla {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x200>;
|
||||
};
|
||||
|
||||
pllb: pllb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8750-pll-clock";
|
||||
clocks = <&ref25>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x204>;
|
||||
};
|
||||
|
||||
pllc: pllc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x208>;
|
||||
};
|
||||
|
||||
plld: plld {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x20c>;
|
||||
};
|
||||
|
||||
plle: plle {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x210>;
|
||||
};
|
||||
|
||||
pllf: pllf {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x214>;
|
||||
};
|
||||
|
||||
pllg: pllg {
|
||||
#clock-cells = <0>;
|
||||
compatible = "wm,wm8850-pll-clock";
|
||||
clocks = <&ref24>;
|
||||
reg = <0x218>;
|
||||
};
|
||||
|
||||
clkarm: arm {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&plla>;
|
||||
divisor-reg = <0x300>;
|
||||
};
|
||||
|
||||
clkahb: ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x304>;
|
||||
};
|
||||
|
||||
clkapb: apb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&pllb>;
|
||||
divisor-reg = <0x320>;
|
||||
};
|
||||
|
||||
clkddr: ddr {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
clocks = <&plld>;
|
||||
divisor-reg = <0x310>;
|
||||
};
|
||||
|
||||
clkuart0: uart0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "via,vt8500-device-clock";
|
||||
|
@ -178,32 +252,36 @@ uhci@d8008d00 {
|
|||
interrupts = <26>;
|
||||
};
|
||||
|
||||
uart0: uart@d8200000 {
|
||||
uart0: serial@d8200000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd8200000 0x1040>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clkuart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@d82b0000 {
|
||||
uart1: serial@d82b0000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd82b0000 0x1040>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clkuart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@d8210000 {
|
||||
uart2: serial@d8210000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd8210000 0x1040>;
|
||||
interrupts = <47>;
|
||||
clocks = <&clkuart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@d82c0000 {
|
||||
uart3: serial@d82c0000 {
|
||||
compatible = "via,vt8500-uart";
|
||||
reg = <0xd82c0000 0x1040>;
|
||||
interrupts = <50>;
|
||||
clocks = <&clkuart3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@d8100000 {
|
||||
|
|
Loading…
Reference in a new issue