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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains but we will also use it for 9-bit constrains on MIPS R6 so we rename it to something more appropriate. Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
parent
a7e07b1ae5
commit
94bfb75ace
9 changed files with 93 additions and 93 deletions
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@ -54,7 +54,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \
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" sc %0, %1 \n" \
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" beqzl %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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int temp; \
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@ -66,7 +66,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \
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" " #asm_op " %0, %2 \n" \
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" sc %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!temp)); \
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} else { \
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@ -97,7 +97,7 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF12_ASM() (v->counter) \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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int temp; \
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@ -110,7 +110,7 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \
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" sc %0, %2 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF12_ASM() (v->counter) \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!result)); \
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\
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@ -171,8 +171,8 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF12_ASM() (v->counter)
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: "Ir" (i), GCC_OFF12_ASM() (v->counter)
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
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: "memory");
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} else if (kernel_uses_llsc) {
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int temp;
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@ -190,7 +190,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF12_ASM() (v->counter)
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i));
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} else {
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unsigned long flags;
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@ -333,7 +333,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \
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" scd %0, %1 \n" \
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" beqzl %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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long temp; \
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@ -345,7 +345,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \
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" " #asm_op " %0, %2 \n" \
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" scd %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!temp)); \
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} else { \
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@ -376,7 +376,7 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF12_ASM() (v->counter) \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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long temp; \
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@ -389,8 +389,8 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \
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" scd %0, %2 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"=" GCC_OFF12_ASM() (v->counter) \
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: "Ir" (i), GCC_OFF12_ASM() (v->counter) \
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"=" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
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: "memory"); \
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} while (unlikely(!result)); \
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\
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@ -452,8 +452,8 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"=" GCC_OFF12_ASM() (v->counter)
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: "Ir" (i), GCC_OFF12_ASM() (v->counter)
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"=" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
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: "memory");
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} else if (kernel_uses_llsc) {
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long temp;
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@ -471,7 +471,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF12_ASM() (v->counter)
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i));
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} else {
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unsigned long flags;
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@ -79,8 +79,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=" GCC_OFF12_ASM() (*m)
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: "ir" (1UL << bit), GCC_OFF12_ASM() (*m));
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: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));
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#ifdef CONFIG_CPU_MIPSR2
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} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
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do {
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@ -88,7 +88,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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" " __LL "%0, %1 # set_bit \n"
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" " __INS "%0, %3, %2, 1 \n"
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" " __SC "%0, %1 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (bit), "r" (~0));
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} while (unlikely(!temp));
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#endif /* CONFIG_CPU_MIPSR2 */
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@ -100,7 +100,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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" or %0, %2 \n"
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" " __SC "%0, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (1UL << bit));
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} while (unlikely(!temp));
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} else
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@ -131,7 +131,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (~(1UL << bit)));
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#ifdef CONFIG_CPU_MIPSR2
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} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
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@ -140,7 +140,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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" " __LL "%0, %1 # clear_bit \n"
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" " __INS "%0, $0, %2, 1 \n"
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" " __SC "%0, %1 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (bit));
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} while (unlikely(!temp));
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#endif /* CONFIG_CPU_MIPSR2 */
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@ -152,7 +152,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (~(1UL << bit)));
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} while (unlikely(!temp));
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} else
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@ -197,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (1UL << bit));
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} else if (kernel_uses_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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@ -210,7 +210,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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" xor %0, %2 \n"
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" " __SC "%0, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
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: "ir" (1UL << bit));
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} while (unlikely(!temp));
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} else
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@ -245,7 +245,7 @@ static inline int test_and_set_bit(unsigned long nr,
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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} else if (kernel_uses_llsc) {
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@ -259,7 +259,7 @@ static inline int test_and_set_bit(unsigned long nr,
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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} while (unlikely(!res));
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@ -313,7 +313,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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} while (unlikely(!res));
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@ -355,7 +355,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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#ifdef CONFIG_CPU_MIPSR2
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@ -369,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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" " __EXT "%2, %0, %3, 1 \n"
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" " __INS "%0, $0, %3, 1 \n"
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" " __SC "%0, %1 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "ir" (bit)
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: "memory");
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} while (unlikely(!temp));
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@ -386,7 +386,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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" xor %2, %3 \n"
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" " __SC "%2, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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} while (unlikely(!res));
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@ -428,7 +428,7 @@ static inline int test_and_change_bit(unsigned long nr,
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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} else if (kernel_uses_llsc) {
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@ -442,7 +442,7 @@ static inline int test_and_change_bit(unsigned long nr,
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" xor %2, %0, %3 \n"
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" " __SC "\t%2, %1 \n"
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" .set mips0 \n"
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: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: "memory");
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} while (unlikely(!res));
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@ -31,8 +31,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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" sc %2, %1 \n"
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" beqzl %2, 1b \n"
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" .set mips0 \n"
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: "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)
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: GCC_OFF12_ASM() (*m), "Jr" (val)
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: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
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: "memory");
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} else if (kernel_uses_llsc) {
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unsigned long dummy;
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@ -46,9 +46,9 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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" .set arch=r4000 \n"
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" sc %2, %1 \n"
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" .set mips0 \n"
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: "=&r" (retval), "=" GCC_OFF12_ASM() (*m),
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: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
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"=&r" (dummy)
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: GCC_OFF12_ASM() (*m), "Jr" (val)
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
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: "memory");
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} while (unlikely(!dummy));
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} else {
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@ -82,8 +82,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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" scd %2, %1 \n"
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" beqzl %2, 1b \n"
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" .set mips0 \n"
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: "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)
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: GCC_OFF12_ASM() (*m), "Jr" (val)
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: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
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: "memory");
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} else if (kernel_uses_llsc) {
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unsigned long dummy;
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@ -95,9 +95,9 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" .set mips0 \n"
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: "=&r" (retval), "=" GCC_OFF12_ASM() (*m),
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: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
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"=&r" (dummy)
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: GCC_OFF12_ASM() (*m), "Jr" (val)
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
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: "memory");
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} while (unlikely(!dummy));
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} else {
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@ -158,8 +158,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
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" beqzl $1, 1b \n" \
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"2: \n" \
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" .set pop \n" \
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: "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \
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: GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \
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: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
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: "memory"); \
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} else if (kernel_uses_llsc) { \
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__asm__ __volatile__( \
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@ -175,8 +175,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
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" beqz $1, 1b \n" \
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" .set pop \n" \
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"2: \n" \
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: "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \
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: GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \
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: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
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: "memory"); \
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} else { \
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unsigned long __flags; \
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||||
|
|
|
@ -17,9 +17,9 @@
|
|||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_MICROMIPS
|
||||
#define GCC_OFF12_ASM() "R"
|
||||
#define GCC_OFF_SMALL_ASM() "R"
|
||||
#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
|
||||
#define GCC_OFF12_ASM() "ZC"
|
||||
#define GCC_OFF_SMALL_ASM() "ZC"
|
||||
#else
|
||||
#error "microMIPS compilation unsupported with GCC older than 4.9"
|
||||
#endif
|
||||
|
|
|
@ -26,8 +26,8 @@ static inline void atomic_scrub(void *va, u32 size)
|
|||
" sc %0, %1 \n"
|
||||
" beqz %0, 1b \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "=" GCC_OFF12_ASM() (*virt_addr)
|
||||
: GCC_OFF12_ASM() (*virt_addr));
|
||||
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)
|
||||
: GCC_OFF_SMALL_ASM() (*virt_addr));
|
||||
|
||||
virt_addr++;
|
||||
}
|
||||
|
|
|
@ -45,8 +45,8 @@
|
|||
" "__UA_ADDR "\t2b, 4b \n" \
|
||||
" .previous \n" \
|
||||
: "=r" (ret), "=&r" (oldval), \
|
||||
"=" GCC_OFF12_ASM() (*uaddr) \
|
||||
: "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \
|
||||
"=" GCC_OFF_SMALL_ASM() (*uaddr) \
|
||||
: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
|
||||
"i" (-EFAULT) \
|
||||
: "memory"); \
|
||||
} else if (cpu_has_llsc) { \
|
||||
|
@ -74,8 +74,8 @@
|
|||
" "__UA_ADDR "\t2b, 4b \n" \
|
||||
" .previous \n" \
|
||||
: "=r" (ret), "=&r" (oldval), \
|
||||
"=" GCC_OFF12_ASM() (*uaddr) \
|
||||
: "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \
|
||||
"=" GCC_OFF_SMALL_ASM() (*uaddr) \
|
||||
: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
|
||||
"i" (-EFAULT) \
|
||||
: "memory"); \
|
||||
} else \
|
||||
|
@ -174,8 +174,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
" "__UA_ADDR "\t1b, 4b \n"
|
||||
" "__UA_ADDR "\t2b, 4b \n"
|
||||
" .previous \n"
|
||||
: "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
|
||||
: GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
|
||||
: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
|
||||
: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
|
||||
"i" (-EFAULT)
|
||||
: "memory");
|
||||
} else if (cpu_has_llsc) {
|
||||
|
@ -203,8 +203,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
" "__UA_ADDR "\t1b, 4b \n"
|
||||
" "__UA_ADDR "\t2b, 4b \n"
|
||||
" .previous \n"
|
||||
: "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
|
||||
: GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
|
||||
: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
|
||||
: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
|
||||
"i" (-EFAULT)
|
||||
: "memory");
|
||||
} else
|
||||
|
|
|
@ -85,8 +85,8 @@ static inline void set_value_reg32(volatile u32 *const addr,
|
|||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
|
||||
: "ir" (~mask), "ir" (value), GCC_OFF12_ASM() (*addr));
|
||||
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
|
||||
: "ir" (~mask), "ir" (value), GCC_OFF_SMALL_ASM() (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -106,8 +106,8 @@ static inline void set_reg32(volatile u32 *const addr,
|
|||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
|
||||
: "ir" (mask), GCC_OFF12_ASM() (*addr));
|
||||
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
|
||||
: "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -127,8 +127,8 @@ static inline void clear_reg32(volatile u32 *const addr,
|
|||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
|
||||
: "ir" (~mask), GCC_OFF12_ASM() (*addr));
|
||||
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
|
||||
: "ir" (~mask), GCC_OFF_SMALL_ASM() (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -148,8 +148,8 @@ static inline void toggle_reg32(volatile u32 *const addr,
|
|||
" "__beqz"%0, 1b \n"
|
||||
" nop \n"
|
||||
" .set pop \n"
|
||||
: "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
|
||||
: "ir" (mask), GCC_OFF12_ASM() (*addr));
|
||||
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
|
||||
: "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -220,8 +220,8 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
|
|||
" .set arch=r4000 \n" \
|
||||
"1: ll %0, %1 #custom_read_reg32 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (tmp), "=" GCC_OFF12_ASM() (*address) \
|
||||
: GCC_OFF12_ASM() (*address))
|
||||
: "=r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
|
||||
: GCC_OFF_SMALL_ASM() (*address))
|
||||
|
||||
#define custom_write_reg32(address, tmp) \
|
||||
__asm__ __volatile__( \
|
||||
|
@ -231,7 +231,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
|
|||
" "__beqz"%0, 1b \n" \
|
||||
" nop \n" \
|
||||
" .set pop \n" \
|
||||
: "=&r" (tmp), "=" GCC_OFF12_ASM() (*address) \
|
||||
: "0" (tmp), GCC_OFF12_ASM() (*address))
|
||||
: "=&r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
|
||||
: "0" (tmp), GCC_OFF_SMALL_ASM() (*address))
|
||||
|
||||
#endif /* __ASM_REGOPS_H__ */
|
||||
|
|
|
@ -275,7 +275,7 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
|
|||
" lbu %[ticket], %[now_serving]\n"
|
||||
"4:\n"
|
||||
".set pop\n" :
|
||||
[ticket_ptr] "=" GCC_OFF12_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
|
||||
[ticket_ptr] "=" GCC_OFF_SMALL_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
|
||||
[now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
|
||||
[my_ticket] "=r"(my_ticket)
|
||||
);
|
||||
|
|
|
@ -89,7 +89,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
|
|||
" subu %[ticket], %[ticket], 1 \n"
|
||||
" .previous \n"
|
||||
" .set pop \n"
|
||||
: [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
|
||||
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
|
||||
[serving_now_ptr] "+m" (lock->h.serving_now),
|
||||
[ticket] "=&r" (tmp),
|
||||
[my_ticket] "=&r" (my_ticket)
|
||||
|
@ -122,7 +122,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
|
|||
" subu %[ticket], %[ticket], 1 \n"
|
||||
" .previous \n"
|
||||
" .set pop \n"
|
||||
: [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
|
||||
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
|
||||
[serving_now_ptr] "+m" (lock->h.serving_now),
|
||||
[ticket] "=&r" (tmp),
|
||||
[my_ticket] "=&r" (my_ticket)
|
||||
|
@ -164,7 +164,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
|
|||
" li %[ticket], 0 \n"
|
||||
" .previous \n"
|
||||
" .set pop \n"
|
||||
: [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
|
||||
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
|
||||
[ticket] "=&r" (tmp),
|
||||
[my_ticket] "=&r" (tmp2),
|
||||
[now_serving] "=&r" (tmp3)
|
||||
|
@ -188,7 +188,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
|
|||
" li %[ticket], 0 \n"
|
||||
" .previous \n"
|
||||
" .set pop \n"
|
||||
: [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
|
||||
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
|
||||
[ticket] "=&r" (tmp),
|
||||
[my_ticket] "=&r" (tmp2),
|
||||
[now_serving] "=&r" (tmp3)
|
||||
|
@ -235,8 +235,8 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
|
|||
" beqzl %1, 1b \n"
|
||||
" nop \n"
|
||||
" .set reorder \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} else {
|
||||
do {
|
||||
|
@ -245,8 +245,8 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
|
|||
" bltz %1, 1b \n"
|
||||
" addu %1, 1 \n"
|
||||
"2: sc %1, %0 \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} while (unlikely(!tmp));
|
||||
}
|
||||
|
@ -269,8 +269,8 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
|
|||
" sub %1, 1 \n"
|
||||
" sc %1, %0 \n"
|
||||
" beqzl %1, 1b \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} else {
|
||||
do {
|
||||
|
@ -278,8 +278,8 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
|
|||
"1: ll %1, %2 # arch_read_unlock \n"
|
||||
" sub %1, 1 \n"
|
||||
" sc %1, %0 \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} while (unlikely(!tmp));
|
||||
}
|
||||
|
@ -299,8 +299,8 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
|
|||
" beqzl %1, 1b \n"
|
||||
" nop \n"
|
||||
" .set reorder \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} else {
|
||||
do {
|
||||
|
@ -309,8 +309,8 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
|
|||
" bnez %1, 1b \n"
|
||||
" lui %1, 0x8000 \n"
|
||||
"2: sc %1, %0 \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} while (unlikely(!tmp));
|
||||
}
|
||||
|
@ -349,8 +349,8 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
|
|||
__WEAK_LLSC_MB
|
||||
" li %2, 1 \n"
|
||||
"2: \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} else {
|
||||
__asm__ __volatile__(
|
||||
|
@ -366,8 +366,8 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
|
|||
__WEAK_LLSC_MB
|
||||
" li %2, 1 \n"
|
||||
"2: \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
|
@ -393,8 +393,8 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
|
|||
" li %2, 1 \n"
|
||||
" .set reorder \n"
|
||||
"2: \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} else {
|
||||
do {
|
||||
|
@ -406,9 +406,9 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
|
|||
" sc %1, %0 \n"
|
||||
" li %2, 1 \n"
|
||||
"2: \n"
|
||||
: "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp),
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
|
||||
"=&r" (ret)
|
||||
: GCC_OFF12_ASM() (rw->lock)
|
||||
: GCC_OFF_SMALL_ASM() (rw->lock)
|
||||
: "memory");
|
||||
} while (unlikely(!tmp));
|
||||
|
||||
|
|
Loading…
Reference in a new issue