ARM: EXYNOS: add support for EXYNOS5250 SoC
This patch add support for EXYNOS5250 SoC has two Cortex-A15 cores. Since actually, most codes in mach-exynos/ are used commonly for EXYNOS4 and EXYNOS5 the EXYNOS5/EXYNOS5250 has been implemented in mach-exynos/. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
parent
171c067c1a
commit
94c7ca71c4
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@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
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machine-$(CONFIG_ARCH_S5PC100) := s5pc100
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machine-$(CONFIG_ARCH_S5PV210) := s5pv210
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machine-$(CONFIG_ARCH_EXYNOS4) := exynos
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machine-$(CONFIG_ARCH_EXYNOS5) := exynos
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machine-$(CONFIG_ARCH_SA1100) := sa1100
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machine-$(CONFIG_ARCH_SHARK) := shark
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machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
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@ -49,9 +49,12 @@
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static const char name_exynos4210[] = "EXYNOS4210";
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static const char name_exynos4212[] = "EXYNOS4212";
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static const char name_exynos4412[] = "EXYNOS4412";
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static const char name_exynos5250[] = "EXYNOS5250";
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static void exynos4_map_io(void);
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static void exynos5_map_io(void);
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static void exynos4_init_clocks(int xtal);
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static void exynos5_init_clocks(int xtal);
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static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
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static int exynos_init(void);
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@ -80,6 +83,14 @@ static struct cpu_table cpu_ids[] __initdata = {
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.init_uarts = exynos_init_uarts,
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.init = exynos_init,
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.name = name_exynos4412,
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}, {
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.idcode = EXYNOS5250_SOC_ID,
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.idmask = EXYNOS5_SOC_MASK,
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.map_io = exynos5_map_io,
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.init_clocks = exynos5_init_clocks,
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.init_uarts = exynos_init_uarts,
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.init = exynos_init,
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.name = name_exynos5250,
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},
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};
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@ -88,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
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static struct map_desc exynos_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
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.pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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},
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};
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
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.length = SZ_64K,
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@ -141,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
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.length = SZ_512K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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.length = SZ_128K,
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@ -206,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
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},
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};
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static struct map_desc exynos5_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSTIMER,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSRAM,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
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.length = 144 * SZ_1K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
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.pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
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.length = SZ_512K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_CPU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_DIST,
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.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
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.length = SZ_64K,
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.type = MT_DEVICE,
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},
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};
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void exynos4_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, S5P_SWRESET);
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}
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void exynos5_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, EXYNOS_SWRESET);
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}
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/*
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* exynos_map_io
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*
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@ -261,6 +341,16 @@ static void __init exynos4_map_io(void)
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s5p_hdmi_setname("exynos4-hdmi");
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}
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static void __init exynos5_map_io(void)
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{
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iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
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/* The I2C bus controllers are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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s3c_i2c2_setname("s3c2440-i2c");
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}
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static void __init exynos4_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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@ -277,6 +367,17 @@ static void __init exynos4_init_clocks(int xtal)
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exynos4_setup_clocks();
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}
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static void __init exynos5_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s5p_register_clocks(xtal);
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exynos5_register_clocks();
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exynos5_setup_clocks();
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}
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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@ -420,24 +521,59 @@ void __init exynos4_init_irq(void)
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s5p_init_irq(NULL, 0);
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}
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void __init exynos5_init_irq(void)
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{
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int irq;
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gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
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for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
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combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
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COMBINER_IRQ(irq, 0));
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combiner_cascade_irq(irq, IRQ_SPI(irq));
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}
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/*
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* The parameters of s5p_init_irq() are for VIC init.
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* Theses parameters should be NULL and 0 because EXYNOS4
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* uses GIC instead of VIC.
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*/
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s5p_init_irq(NULL, 0);
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}
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struct bus_type exynos4_subsys = {
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.name = "exynos4-core",
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.dev_name = "exynos4-core",
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};
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struct bus_type exynos5_subsys = {
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.name = "exynos5-core",
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.dev_name = "exynos5-core",
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};
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static struct device exynos4_dev = {
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.bus = &exynos4_subsys,
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};
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static int __init exynos4_core_init(void)
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static struct device exynos5_dev = {
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.bus = &exynos5_subsys,
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};
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static int __init exynos_core_init(void)
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{
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return subsys_system_register(&exynos4_subsys, NULL);
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if (soc_is_exynos5250())
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return subsys_system_register(&exynos5_subsys, NULL);
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else
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return subsys_system_register(&exynos4_subsys, NULL);
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}
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core_initcall(exynos4_core_init);
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core_initcall(exynos_core_init);
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#ifdef CONFIG_CACHE_L2X0
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static int __init exynos4_l2x0_cache_init(void)
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{
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if (soc_is_exynos5250())
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return 0;
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/* TAG, Data Latency Control: 2cycle */
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__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
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@ -457,14 +593,42 @@ static int __init exynos4_l2x0_cache_init(void)
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return 0;
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}
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early_initcall(exynos4_l2x0_cache_init);
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#endif
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static int __init exynos5_l2_cache_init(void)
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{
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unsigned int val;
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if (!soc_is_exynos5250())
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return 0;
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asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #(1 << 2)\n" /* cache disable */
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"mcr p15, 0, %0, c1, c0, 0\n"
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"mrc p15, 1, %0, c9, c0, 2\n"
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: "=r"(val));
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val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
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asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
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asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #(1 << 2)\n" /* cache enable */
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"mcr p15, 0, %0, c1, c0, 0\n"
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: : "r"(val));
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return 0;
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}
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early_initcall(exynos5_l2_cache_init);
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static int __init exynos_init(void)
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{
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printk(KERN_INFO "EXYNOS: Initializing architecture\n");
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return device_register(&exynos4_dev);
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if (soc_is_exynos5250())
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return device_register(&exynos5_dev);
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else
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return device_register(&exynos4_dev);
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}
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/* uart registration process */
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@ -673,6 +837,9 @@ static int __init exynos4_init_irq_eint(void)
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{
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int irq;
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if (soc_is_exynos5250())
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return 0;
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for (irq = 0 ; irq <= 31 ; irq++) {
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irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
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handle_level_irq);
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@ -16,7 +16,9 @@ extern struct sys_timer exynos4_timer;
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void exynos_init_io(struct map_desc *mach_desc, int size);
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void exynos4_init_irq(void);
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void exynos5_init_irq(void);
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void exynos4_restart(char mode, const char *cmd);
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void exynos5_restart(char mode, const char *cmd);
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#ifdef CONFIG_ARCH_EXYNOS4
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void exynos4_register_clocks(void);
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@ -27,6 +29,15 @@ void exynos4_setup_clocks(void);
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#define exynos4_setup_clocks()
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#endif
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#ifdef CONFIG_ARCH_EXYNOS5
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void exynos5_register_clocks(void);
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void exynos5_setup_clocks(void);
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#else
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#define exynos5_register_clocks()
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#define exynos5_setup_clocks()
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#endif
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#ifdef CONFIG_CPU_EXYNOS4210
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void exynos4210_register_clocks(void);
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@ -25,6 +25,7 @@
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#define EXYNOS4_PA_SYSRAM0 0x02025000
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#define EXYNOS4_PA_SYSRAM1 0x02020000
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#define EXYNOS5_PA_SYSRAM 0x02020000
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#define EXYNOS4_PA_FIMC0 0x11800000
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#define EXYNOS4_PA_FIMC1 0x11810000
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@ -44,14 +45,23 @@
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#define EXYNOS4_PA_ONENAND 0x0C000000
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#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
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#define EXYNOS4_PA_CHIPID 0x10000000
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS4_PA_SYSCON 0x10010000
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#define EXYNOS5_PA_SYSCON 0x10050100
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#define EXYNOS4_PA_PMU 0x10020000
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#define EXYNOS5_PA_PMU 0x10040000
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#define EXYNOS4_PA_CMU 0x10030000
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#define EXYNOS5_PA_CMU 0x10010000
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#define EXYNOS4_PA_SYSTIMER 0x10050000
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#define EXYNOS5_PA_SYSTIMER 0x101C0000
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#define EXYNOS4_PA_WATCHDOG 0x10060000
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#define EXYNOS5_PA_WATCHDOG 0x101D0000
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#define EXYNOS4_PA_RTC 0x10070000
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#define EXYNOS4_PA_KEYPAD 0x100A0000
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@ -59,9 +69,12 @@
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#define EXYNOS4_PA_DMC0 0x10400000
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#define EXYNOS4_PA_COMBINER 0x10440000
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#define EXYNOS5_PA_COMBINER 0x10440000
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#define EXYNOS4_PA_GIC_CPU 0x10480000
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#define EXYNOS4_PA_GIC_DIST 0x10490000
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#define EXYNOS5_PA_GIC_CPU 0x10480000
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#define EXYNOS5_PA_GIC_DIST 0x10490000
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#define EXYNOS4_PA_COREPERI 0x10500000
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#define EXYNOS4_PA_TWD 0x10500600
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@ -92,7 +105,6 @@
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#define EXYNOS4_PA_SPI1 0x13930000
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#define EXYNOS4_PA_SPI2 0x13940000
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#define EXYNOS4_PA_GPIO1 0x11400000
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#define EXYNOS4_PA_GPIO2 0x11000000
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#define EXYNOS4_PA_GPIO3 0x03860000
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@ -110,6 +122,7 @@
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#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS5_PA_SROMC 0x12250000
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#define EXYNOS4_PA_EHCI 0x12580000
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#define EXYNOS4_PA_OHCI 0x12590000
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@ -117,6 +130,7 @@
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#define EXYNOS4_PA_MFC 0x13400000
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#define EXYNOS4_PA_UART 0x13800000
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#define EXYNOS5_PA_UART 0x12C00000
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#define EXYNOS4_PA_VP 0x12C00000
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#define EXYNOS4_PA_MIXER 0x12C10000
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@ -125,6 +139,7 @@
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#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
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#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
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#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
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#define EXYNOS4_PA_ADC 0x13910000
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#define EXYNOS4_PA_ADC1 0x13911000
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@ -134,8 +149,10 @@
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#define EXYNOS4_PA_SPDIF 0x139B0000
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#define EXYNOS4_PA_TIMER 0x139D0000
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#define EXYNOS5_PA_TIMER 0x12DD0000
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#define EXYNOS4_PA_SDRAM 0x40000000
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#define EXYNOS5_PA_SDRAM 0x40000000
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/* Compatibiltiy Defines */
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||||
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||||
|
|
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|||
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|
@ -31,6 +31,7 @@
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|||
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
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||||
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||||
#define S5P_SWRESET S5P_PMUREG(0x0400)
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#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
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||||
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||||
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
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||||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
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||||
|
|
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|||
|
|
@ -9,8 +9,8 @@ config PLAT_S5P
|
|||
bool
|
||||
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
|
||||
default y
|
||||
select ARM_VIC if !ARCH_EXYNOS4
|
||||
select ARM_GIC if ARCH_EXYNOS4
|
||||
select ARM_VIC if !ARCH_EXYNOS
|
||||
select ARM_GIC if ARCH_EXYNOS
|
||||
select GIC_NON_BANKED if ARCH_EXYNOS4
|
||||
select NO_IOPORT
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
|
|||
#define EXYNOS4412_CPU_ID 0xE4412200
|
||||
#define EXYNOS4_CPU_MASK 0xFFFE0000
|
||||
|
||||
#define EXYNOS5250_SOC_ID 0x43520000
|
||||
#define EXYNOS5_SOC_MASK 0xFFFFF000
|
||||
|
||||
#define IS_SAMSUNG_CPU(name, id, mask) \
|
||||
static inline int is_samsung_##name(void) \
|
||||
{ \
|
||||
|
|
@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
|
|||
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
|
||||
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
|
||||
|
|
@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
|
|||
#define EXYNOS4210_REV_1_0 (0x10)
|
||||
#define EXYNOS4210_REV_1_1 (0x11)
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5250)
|
||||
# define soc_is_exynos5250() is_samsung_exynos5250()
|
||||
#else
|
||||
# define soc_is_exynos5250() 0
|
||||
#endif
|
||||
|
||||
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
|
||||
|
||||
#ifndef MHZ
|
||||
|
|
|
|||
Loading…
Reference in New Issue