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drm/amd/display: Fix DP MST timeslot issue when fallback happened
[ Upstream commit 20c6168b3c
]
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
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commit
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1 changed files with 7 additions and 1 deletions
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@ -2857,8 +2857,14 @@ bool perform_link_training_with_retries(
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skip_video_pattern);
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skip_video_pattern);
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/* Transmit idle pattern once training successful. */
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/* Transmit idle pattern once training successful. */
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if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low)
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if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
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dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
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dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
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/* Update verified link settings to current one
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* Because DPIA LT might fallback to lower link setting.
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*/
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link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
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link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
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}
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} else {
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} else {
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status = dc_link_dp_perform_link_training(link,
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status = dc_link_dp_perform_link_training(link,
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&pipe_ctx->link_res,
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&pipe_ctx->link_res,
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